x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

11 files changed, 70 insertions, 65 deletions

diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index fb0dc877f4..11c44934f4 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -105,7 +105,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 
 static int acpi_sci_irq(void)
 {
-	const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+	u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
 	int scis;
 	static int sci_irq;
 
diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
index d3a23770dd..1982c278d1 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
@@ -34,8 +34,11 @@
 /* Southbridge internal device MEM BARs (Set to match FSP settings) */
 #define DEFAULT_IBASE		0xfed08000
 #define DEFAULT_PBASE		0xfed03000
+#ifndef __ACPI__
+#define DEFAULT_RCBA		((u8 *)0xfed1c000)
+#else
 #define DEFAULT_RCBA		0xfed1c000
-
+#endif
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
 
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index a45254a8af..e06c8d6bee 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -353,20 +353,20 @@ void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
 #define PCU_SMB_CLK_PAD			88
 #define PCU_SMB_DATA_PAD		90
 
-static inline unsigned int score_pconf0(int pad_num)
+static inline uint32_t *score_pconf0(int pad_num)
 {
-	return GPSCORE_PAD_BASE + pad_num * 16;
+	return (uint32_t *)(GPSCORE_PAD_BASE + pad_num * 16);
 }
 
-static inline unsigned int ssus_pconf0(int pad_num)
+static inline uint32_t *ssus_pconf0(int pad_num)
 {
-	return GPSSUS_PAD_BASE + pad_num * 16;
+	return (uint32_t *)(GPSSUS_PAD_BASE + pad_num * 16);
 }
 
 static inline void score_select_func(int pad, int func)
 {
 	uint32_t reg;
-	uint32_t pconf0_addr = score_pconf0(pad);
+	uint32_t *pconf0_addr = score_pconf0(pad);
 
 	reg = read32(pconf0_addr);
 	reg &= ~0x7;
@@ -377,7 +377,7 @@ static inline void score_select_func(int pad, int func)
 static inline void ssus_select_func(int pad, int func)
 {
 	uint32_t reg;
-	uint32_t pconf0_addr = ssus_pconf0(pad);
+	uint32_t *pconf0_addr = ssus_pconf0(pad);
 
 	reg = read32(pconf0_addr);
 	reg &= ~0x7;
@@ -390,14 +390,14 @@ static inline void ssus_select_func(int pad, int func)
 /* These functions require that the input pad be configured as an input GPIO */
 static inline int score_get_gpio(int pad)
 {
-	uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
+	uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
 
 	return read32(val_addr) & PAD_VAL_HIGH;
 }
 
 static inline int ssus_get_gpio(int pad)
 {
-	uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
+	uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
 
 	return read32(val_addr) & PAD_VAL_HIGH;
 }
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index e8f5572ef7..843e7410d7 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -63,7 +63,7 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
  */
 static void enable_spi_prefetch(void)
 {
-	uint32_t bcr = SPI_BASE_ADDRESS + BCR;
+	u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
 	/* Enable caching and prefetching in the SPI controller. */
 	write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH);
 }
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index b202f0061f..f4159c9588 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -103,7 +103,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
 {
 	const struct soc_gpio_map *config;
 	int gpio = 0;
-	u32 reg, pad_conf0;
+	u32 reg, pad_conf0, *regmmio;
 	u8 set, bit;
 
 	u32 use_sel[4] = {0};
@@ -138,7 +138,8 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
 		}
 
 		/* Pad configuration registers */
-		reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio];
+		regmmio = (u32 *)(bank->pad_base + 16 *
+				  bank->gpio_to_pad[gpio]);
 
 		/* Add correct func to GPIO pad config */
 		pad_conf0 = config->pad_conf0;
@@ -152,13 +153,14 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
 		}
 
 #ifdef GPIO_DEBUG
-		printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n",
-		       reg, pad_conf0, config->pad_conf1, config->pad_val);
+		printk(BIOS_DEBUG, "Write Pad: Base(%p) - %x %x %x\n",
+		       regmmio, pad_conf0, config->pad_conf1, config->pad_val);
 #endif
 
-		write32(reg + PAD_CONF0_REG, pad_conf0);
-		write32(reg + PAD_CONF1_REG, config->pad_conf1);
-		write32(reg + PAD_VAL_REG, config->pad_val);
+		write32(regmmio + (PAD_CONF0_REG/sizeof(u32)), pad_conf0);
+		write32(regmmio + (PAD_CONF1_REG/sizeof(u32)),
+			config->pad_conf1);
+		write32(regmmio + (PAD_VAL_REG/sizeof(u32)), config->pad_val);
 	}
 
 	if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -215,7 +217,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
 static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
 			const struct gpio_bank *bank)
 {
-	u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
+	u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
 	u32 val;
 	int i;
 
@@ -223,10 +225,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
 	for (i=0; i<4; ++i) {
 		val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
 		      dirq[i * 4 + 1] << 8  | dirq[i * 4];
-		write32(reg + i * 4, val);
+		write32(reg + i, val);
 #ifdef GPIO_DEBUG
 		printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
-			reg + i * 4, val);
+		       reg + i, val);
 #endif
 	}
 }
@@ -299,7 +301,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
                            uint32_t pconf0, uint32_t pad_val)
 {
 	uint32_t reg;
-	uint32_t pad_addr;
+	uint32_t *pad_addr;
 	if (ssus_gpio)
 		pad_addr = ssus_pconf0(gpssus_gpio_to_pad[gpio_num]);
 	else
@@ -321,7 +323,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
 	 */
 	reg = PAD_CONFIG0_DEFAULT;
 	reg |= pconf0 & 0x787;
-	write32(pad_addr + PAD_CONF0_REG, reg);
+	write32(pad_addr + (PAD_CONF0_REG/sizeof(u32)), reg);
 
 	/*
 	 * Pad Value Register
@@ -329,10 +331,10 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
 	 * 1: output enable (0 is enabled)
 	 * 2: input enable  (0 is enabled)
 	 */
-	reg = read32(pad_addr + PAD_VAL_REG);
+	reg = read32(pad_addr + (PAD_VAL_REG/sizeof(u32)));
 	reg &= ~0x7;
 	reg |= pad_val & 0x7;
-	write32(pad_addr + PAD_VAL_REG, reg);
+	write32(pad_addr + (PAD_VAL_REG/sizeof(u32)), reg);
 }
 
 /** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO
diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c
index f892b20a6b..eee7c64692 100644
--- a/src/soc/intel/fsp_baytrail/iosf.c
+++ b/src/soc/intel/fsp_baytrail/iosf.c
@@ -29,11 +29,11 @@
 
 static inline void write_iosf_reg(int reg, uint32_t value)
 {
-	write32(IOSF_PCI_BASE + reg, value);
+	write32((u32 *)(IOSF_PCI_BASE + reg), value);
 }
 static inline uint32_t read_iosf_reg(int reg)
 {
-	return read32(IOSF_PCI_BASE + reg);
+	return read32((u32 *)(IOSF_PCI_BASE + reg));
 }
 #else
 static inline void write_iosf_reg(int reg, uint32_t value)
diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c
index aee37261be..8295b692b7 100644
--- a/src/soc/intel/fsp_baytrail/pmutil.c
+++ b/src/soc/intel/fsp_baytrail/pmutil.c
@@ -355,10 +355,10 @@ void clear_pmc_status(void)
 	uint32_t prsts;
 	uint32_t gen_pmcon1;
 
-	prsts = read32(PMC_BASE_ADDRESS + PRSTS);
-	gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+	prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
+	gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
 
 	/* Clear the status bits. The RPS field is cleared on a 0 write. */
-	write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
-	write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+	write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
+	write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
 }
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index e487a25e86..81a02795ab 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -56,7 +56,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
 	/* Read Power State */
 	pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
 	pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
-	gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+	gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
 
 	printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
 		pm1_sts, pm1_cnt, gen_pmcon1);
@@ -118,8 +118,8 @@ static void program_base_addresses(void)
 
 static void spi_init(void)
 {
-	const uint32_t scs = SPI_BASE_ADDRESS + SCS;
-	const uint32_t bcr = SPI_BASE_ADDRESS + BCR;
+	uint32_t *scs = (uint32_t *)(SPI_BASE_ADDRESS + SCS);
+	uint32_t *bcr = (uint32_t *)(SPI_BASE_ADDRESS + BCR);
 	uint32_t reg;
 
 	/* Disable generating SMI when setting WPD bit. */
@@ -135,8 +135,8 @@ static void spi_init(void)
 
 static void baytrail_rtc_init(void)
 {
-	uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0;
-	uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+	uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0);
+	uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32)));
 	int rtc_failed = !!(gen_pmcon1 & RPS);
 
 	if (rtc_failed) {
@@ -144,7 +144,7 @@ static void baytrail_rtc_init(void)
 			"RTC Failure detected.  Resetting Date to %s\n",
 			coreboot_dmi_date);
 
-		write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+		write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS);
 	}
 
 	cmos_init(rtc_failed);
@@ -153,8 +153,8 @@ static void baytrail_rtc_init(void)
 /* Entry from cache-as-ram.inc. */
 void main(FSP_INFO_HEADER *fsp_info_header)
 {
-	const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
-	const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+	uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS);
+	uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2);
 	uint32_t fd_mask = 0;
 	uint32_t fd2_mask = 0;
 
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index d4b3d58350..2a8892d04a 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -67,7 +67,7 @@ void southcluster_smm_clear_state(void)
 
 static void southcluster_smm_route_gpios(void)
 {
-	const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
+	u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
 	const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
 	uint32_t alt_gpio_reg = 0;
 	uint32_t route_reg = gpio_route;
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index d87935b517..878535f534 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -82,17 +82,17 @@ static void sc_enable_ioapic(struct device *dev)
 {
 	int i;
 	u32 reg32;
-	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-	u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f;
+	volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10);
+	u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
 
 	/*
 	 * Enable ACPI I/O and power management.
 	 * Set SCI IRQ to IRQ9
 	 */
 	write32(ilb_base + ILB_OIC, 0x100);  /* AEN */
-	reg32 = read32(ilb_base + ILB_OIC);  /* Read back per BWG */
-	write32(ilb_base + ILB_ACTL, 0);  /* ACTL bit 2:0 SCIS IRQ9 */
+	reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */
+	write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0);  /* ACTL bit 2:0 SCIS IRQ9 */
 
 	*ioapic_index = 0;
 	*ioapic_data = (1 << 25);
@@ -131,7 +131,7 @@ static void sc_enable_serial_irqs(struct device *dev)
 	 * until we understand how it needs to be configured.
 	 */
 	u8 reg8;
-	u32 ibase = pci_read_config32(dev, IBASE) & ~0xF;
+	u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
 
 	/*
 	 * Disable the IOCHK# NMI. Let the NMI handler enable it if it needs.
@@ -259,9 +259,9 @@ static void sc_pirq_init(device_t dev)
 {
 	int i, j;
 	int pirq;
-	const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
-	const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
-	const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+	u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
+	u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20);
+	u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
 	const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
 
 	/* Set up the PIRQ PIC routing based on static config. */
@@ -269,7 +269,7 @@ static void sc_pirq_init(device_t dev)
 			"PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n"
 			"IRQ ");
 	for (i = 0; i < NUM_PIRQS; i++) {
-		write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+		write8(pr_base + i, ir->pic[i]);
 		printk(BIOS_SPEW, "\t%d", ir->pic[i]);
 	}
 	printk(BIOS_SPEW, "\n\n");
@@ -278,7 +278,7 @@ static void sc_pirq_init(device_t dev)
 	printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
 			"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
 	for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
-		write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+		write16(ir_base + i, ir->pcidev[i]);
 
 		/* If the entry is more than just 0, print it out */
 		if(ir->pcidev[i]) {
@@ -372,11 +372,11 @@ static void enable_hpet(void)
 
 static void sc_init(struct device *dev)
 {
-	u32 ibase;
+	u8 *ibase;
 
 	printk(BIOS_DEBUG, "soc: southcluster_init\n");
 
-	ibase = pci_read_config32(dev, IBASE) & ~0xF;
+	ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
 
 	write8(ibase + ILB_MC, 0);
 
@@ -411,8 +411,8 @@ static void sc_init(struct device *dev)
 /* Set bit in function disable register to hide this device. */
 static void sc_disable_devfn(device_t dev)
 {
-	const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
-	const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+	u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
+	u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
 	uint32_t fd_mask = 0;
 	uint32_t fd2_mask = 0;
 
@@ -471,7 +471,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
  * the audio paths work for LPE audio. */
 static void hda_work_around(device_t dev)
 {
-	unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
+	u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
 
 	/* Need to set magic register 0x43 to 0xd7 in config space. */
 	pci_write_config8(dev, 0x43, 0xd7);
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 0c3c63d8da..abcc62cde1 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -193,33 +193,33 @@ static u32 readl_(const void *addr)
 
 static void writeb_(u8 b, const void *addr)
 {
-	write8((unsigned long)addr, b);
+	write8(addr, b);
 	printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
 	       b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 static void writew_(u16 b, const void *addr)
 {
-	write16((unsigned long)addr, b);
+	write16(addr, b);
 	printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
 	       b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 static void writel_(u32 b, const void *addr)
 {
-	write32((unsigned long)addr, b);
+	write32(addr, b);
 	printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
 	       b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
 
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
 
 #endif  /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */