fsp_baytrail: update to add the UPD_DEFAULT_CHECK macro

- Update chipset_fsp_util.c to use the UPD_DEFAULT_CHECK macro.  This
makes the code more standardized and easier to read.
- Update chip.h to use standardized macros

Change-Id: Icbe5ec92b0aa31e21f3dd1593a96b246d83008f7
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7488
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

2 files changed, 171 insertions, 161 deletions

diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
index 65377a62c5..df1d57e471 100644
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -23,6 +23,7 @@
 #define _FSP_BAYTRAIL_CHIP_H_
 
 #include <arch/acpi.h>
+#include <drivers/intel/fsp/fsp_values.h>
 
 /* The devicetree parser expects chip.h to reside directly in the path
  * specified by the devicetree. */
@@ -34,8 +35,8 @@ struct soc_intel_fsp_baytrail_config {
 	/* Spd addresses */
 	uint8_t  PcdMrcInitSPDAddr1;
 	uint8_t  PcdMrcInitSPDAddr2;
-	#define SPD_ADDR_DEFAULT	0x00
-	#define SPD_ADDR_DISABLED	0xFF
+	#define SPD_ADDR_DEFAULT	UPD_SPD_ADDR_DEFAULT
+	#define SPD_ADDR_DISABLED	UPD_SPD_ADDR_DISABLED
 
 	/* SataMode
 	 *  NOTE: These are offset by 1 to set 0 as "use default".  This is so that
@@ -46,9 +47,9 @@ struct soc_intel_fsp_baytrail_config {
 	 *  0x1 "AHCI"
 	 */
 	uint8_t  PcdSataMode;
-	#define SATA_MODE_DEFAULT	0x00
-	#define SATA_MODE_IDE		0x01
-	#define SATA_MODE_AHCI		0x02
+	#define SATA_MODE_DEFAULT	UPD_DEFAULT
+	#define SATA_MODE_IDE		INCREMENT_FOR_DEFAULT(0)
+	#define SATA_MODE_AHCI		INCREMENT_FOR_DEFAULT(1)
 
 	/*
 	 * MrcInitTsegSize
@@ -58,11 +59,11 @@ struct soc_intel_fsp_baytrail_config {
 	 *  0x08, "8 MB"
 	 */
 	uint16_t PcdMrcInitTsegSize;
-	#define TSEG_SIZE_DEFAULT	0
-	#define TSEG_SIZE_1_MB		1
-	#define TSEG_SIZE_2_MB		2
-	#define TSEG_SIZE_4_MB		4
-	#define TSEG_SIZE_8_MB		8
+	#define TSEG_SIZE_DEFAULT	UPD_DEFAULT
+	#define TSEG_SIZE_1_MB		INCREMENT_FOR_DEFAULT(1)
+	#define TSEG_SIZE_2_MB		INCREMENT_FOR_DEFAULT(2)
+	#define TSEG_SIZE_4_MB		INCREMENT_FOR_DEFAULT(4)
+	#define TSEG_SIZE_8_MB		INCREMENT_FOR_DEFAULT(8)
 
 	/*
 	 * MrcInitMmioSize
@@ -71,10 +72,10 @@ struct soc_intel_fsp_baytrail_config {
 	 *  0x800, "2.0 GB"
 	 */
 	uint16_t PcdMrcInitMmioSize;
-	#define MMIO_SIZE_DEFAULT	0x00
-	#define MMIO_SIZE_1_0_GB	0x400
-	#define MMIO_SIZE_1_5_GB	0x600
-	#define MMIO_SIZE_2_0_GB	0x800
+	#define MMIO_SIZE_DEFAULT	UPD_DEFAULT
+	#define MMIO_SIZE_1_0_GB	INCREMENT_FOR_DEFAULT(0x400)
+	#define MMIO_SIZE_1_5_GB	INCREMENT_FOR_DEFAULT(0x600)
+	#define MMIO_SIZE_2_0_GB	INCREMENT_FOR_DEFAULT(0x800)
 
 	/*
 	 * eMMCBootMode
@@ -88,12 +89,12 @@ struct soc_intel_fsp_baytrail_config {
 	 *   0x3 "eMMC 4.5"
 	 */
 	uint8_t PcdeMMCBootMode;
-	#define EMMC_USE_DEFAULT		0
-	#define EMMC_DISABLED			1
-	#define EMMC_AUTO				2
-	#define EMMC_4_1				3
-	#define EMMC_4_5				4
-	#define EMMC_FOLLOWS_DEVICETREE	5
+	#define EMMC_USE_DEFAULT		UPD_DEFAULT
+	#define EMMC_DISABLED			UPD_DISABLE
+	#define EMMC_AUTO			INCREMENT_FOR_DEFAULT(1)
+	#define EMMC_4_1			INCREMENT_FOR_DEFAULT(2)
+	#define EMMC_4_5			INCREMENT_FOR_DEFAULT(3)
+	#define EMMC_FOLLOWS_DEVICETREE		UPD_USE_DEVICETREE
 
 	/*
 	 * IgdDvmt50PreAlloc
@@ -115,23 +116,23 @@ struct soc_intel_fsp_baytrail_config {
 	 *  0x10, "512 MB"
 	 */
 	uint8_t PcdIgdDvmt50PreAlloc;
-	#define IGD_MEMSIZE_DEFAULT	0x00
-	#define IGD_MEMSIZE_32MB	0x01
-	#define IGD_MEMSIZE_64MB	0x02
-	#define IGD_MEMSIZE_96MB	0x03
-	#define IGD_MEMSIZE_128MB	0x04
-	#define IGD_MEMSIZE_160MB	0x05
-	#define IGD_MEMSIZE_192MB	0x06
-	#define IGD_MEMSIZE_224MB	0x07
-	#define IGD_MEMSIZE_256MB	0x08
-	#define IGD_MEMSIZE_288MB	0x09
-	#define IGD_MEMSIZE_320MB	0x0A
-	#define IGD_MEMSIZE_352MB	0x0B
-	#define IGD_MEMSIZE_384MB	0x0C
-	#define IGD_MEMSIZE_416MB	0x0D
-	#define IGD_MEMSIZE_448MB	0x0E
-	#define IGD_MEMSIZE_480MB	0x0F
-	#define IGD_MEMSIZE_512MB	0x10
+	#define IGD_MEMSIZE_DEFAULT	UPD_DEFAULT
+	#define IGD_MEMSIZE_32MB	INCREMENT_FOR_DEFAULT(0x01)
+	#define IGD_MEMSIZE_64MB	INCREMENT_FOR_DEFAULT(0x02)
+	#define IGD_MEMSIZE_96MB	INCREMENT_FOR_DEFAULT(0x03)
+	#define IGD_MEMSIZE_128MB	INCREMENT_FOR_DEFAULT(0x04)
+	#define IGD_MEMSIZE_160MB	INCREMENT_FOR_DEFAULT(0x05)
+	#define IGD_MEMSIZE_192MB	INCREMENT_FOR_DEFAULT(0x06)
+	#define IGD_MEMSIZE_224MB	INCREMENT_FOR_DEFAULT(0x07)
+	#define IGD_MEMSIZE_256MB	INCREMENT_FOR_DEFAULT(0x08)
+	#define IGD_MEMSIZE_288MB	INCREMENT_FOR_DEFAULT(0x09)
+	#define IGD_MEMSIZE_320MB	INCREMENT_FOR_DEFAULT(0x0A)
+	#define IGD_MEMSIZE_352MB	INCREMENT_FOR_DEFAULT(0x0B)
+	#define IGD_MEMSIZE_384MB	INCREMENT_FOR_DEFAULT(0x0C)
+	#define IGD_MEMSIZE_416MB	INCREMENT_FOR_DEFAULT(0x0D)
+	#define IGD_MEMSIZE_448MB	INCREMENT_FOR_DEFAULT(0x0E)
+	#define IGD_MEMSIZE_480MB	INCREMENT_FOR_DEFAULT(0x0F)
+	#define IGD_MEMSIZE_512MB	INCREMENT_FOR_DEFAULT(0x10)
 	#define IGD_MEMSIZE_MULTIPLIER	32
 
 	/*
@@ -140,10 +141,10 @@ struct soc_intel_fsp_baytrail_config {
 	 * Selection 0x3 , "512 MB"
 	 */
 	uint8_t PcdApertureSize;
-	#define APERTURE_SIZE_DEFAULT	0
-	#define APERTURE_SIZE_128MB		1
-	#define APERTURE_SIZE_256MB		2
-	#define APERTURE_SIZE_512MB		3
+	#define APERTURE_SIZE_DEFAULT	UPD_DEFAULT
+	#define APERTURE_SIZE_128MB		INCREMENT_FOR_DEFAULT(1)
+	#define APERTURE_SIZE_256MB		INCREMENT_FOR_DEFAULT(2)
+	#define APERTURE_SIZE_512MB		INCREMENT_FOR_DEFAULT(3)
 	#define APERTURE_SIZE_BASE		64
 
 	/*
@@ -151,130 +152,171 @@ struct soc_intel_fsp_baytrail_config {
 	 * Selection 0x2 , "2 MB"
 	 */
 	uint8_t PcdGttSize;
-	#define GTT_SIZE_DEFAULT	0
-	#define GTT_SIZE_1MB		1
-	#define GTT_SIZE_2MB		2
+	#define GTT_SIZE_DEFAULT	UPD_DEFAULT
+	#define GTT_SIZE_1MB		INCREMENT_FOR_DEFAULT(1)
+	#define GTT_SIZE_2MB		INCREMENT_FOR_DEFAULT(2)
 
 	/*
 	 *  Enable PCI Mode for LPSS SIO devices.
 	 *  If disabled, LPSS SIO devices will run in ACPI mode.
 	 */
 	uint8_t PcdLpssSioEnablePciMode;
-	#define LPSS_PCI_MODE_DEFAULT	0x00
-	#define LPSS_PCI_MODE_DISABLE	0x01
-	#define LPSS_PCI_MODE_ENABLE	0x02
+	#define LPSS_PCI_MODE_DEFAULT	UPD_DEFAULT
+	#define LPSS_PCI_MODE_DISABLE	UPD_DISABLE
+	#define LPSS_PCI_MODE_ENABLE	UPD_ENABLE
 
 	/* modifiers for various enables */
-	uint8_t  AzaliaAutoEnable;
-	#define AZALIA_FOLLOWS_DEVICETREE	0
-	#define AZALIA_FSP_AUTO_ENABLE		1
+	uint8_t AzaliaAutoEnable;
+	#define AZALIA_FOLLOWS_DEVICETREE	UPD_USE_DEVICETREE
+	#define AZALIA_FSP_AUTO_ENABLE		UPD_ENABLE
 
-	uint8_t  LpeAcpiModeEnable;
-	#define LPE_ACPI_MODE_DISABLED	1
-	#define LPE_ACPI_MODE_ENABLED	2
+	uint8_t LpeAcpiModeEnable;
+	#define LPE_ACPI_MODE_DISABLED	UPD_DISABLE
+	#define LPE_ACPI_MODE_ENABLED	UPD_ENABLE
 
 	uint32_t SerialDebugPortAddress;
-	#define  SerialDebugPortAddress_DEFAULT 0
+	#define  SerialDebugPortAddress_DEFAULT	UPD_DEFAULT
 
 	uint8_t  SerialDebugPortType;
-	#define  SERIAL_DEBUG_PORT_DEFAULT      0
-	#define  SERIAL_DEBUG_PORT_TYPE_NONE    1
-	#define  SERIAL_DEBUG_PORT_TYPE_IO      2
-	#define  SERIAL_DEBUG_PORT_TYPE_MMIO    3
+	#define  SERIAL_DEBUG_PORT_DEFAULT	UPD_DEFAULT
+	#define  SERIAL_DEBUG_PORT_TYPE_NONE	INCREMENT_FOR_DEFAULT(0)
+	#define  SERIAL_DEBUG_PORT_TYPE_IO	INCREMENT_FOR_DEFAULT(1)
+	#define  SERIAL_DEBUG_PORT_TYPE_MMIO	INCREMENT_FOR_DEFAULT(2)
 
 	uint8_t  PcdMrcDebugMsg;
-	#define  MRC_DEBUG_MSG_DEFAULT          0
-	#define  MRC_DEBUG_MSG_DISABLE          1
-	#define  MRC_DEBUG_MSG_ENABLE           2
+	#define  MRC_DEBUG_MSG_DEFAULT	UPD_DEFAULT
+	#define  MRC_DEBUG_MSG_DISABLE	UPD_DISABLE
+	#define  MRC_DEBUG_MSG_ENABLE	UPD_ENABLE
 
 	uint8_t  PcdSccEnablePciMode;
-	#define  SCC_PCI_MODE_DEFAULT           0
-	#define  SCC_PCI_MODE_DISABLE           1
-	#define  SCC_PCI_MODE_ENABLE            2
+	#define  SCC_PCI_MODE_DEFAULT	UPD_DEFAULT
+	#define  SCC_PCI_MODE_DISABLE	UPD_DISABLE
+	#define  SCC_PCI_MODE_ENABLE	UPD_ENABLE
 
 	uint8_t  IgdRenderStandby;
-	#define  IGD_RENDER_STANDBY_DEFAULT     0
-	#define  IGD_RENDER_STANDBY_DISABLE     1
-	#define  IGD_RENDER_STANDBY_ENABLE      2
+	#define  IGD_RENDER_STANDBY_DEFAULT	UPD_DEFAULT
+	#define  IGD_RENDER_STANDBY_DISABLE	UPD_DISABLE
+	#define  IGD_RENDER_STANDBY_ENABLE	UPD_ENABLE
 
 	uint8_t  TxeUmaEnable;
-	#define  TXE_UMA_DEFAULT                0
-	#define  TXE_UMA_DISABLE                1
-	#define  TXE_UMA_ENABLE                 2
+	#define  TXE_UMA_DEFAULT	UPD_DEFAULT
+	#define  TXE_UMA_DISABLE	UPD_DISABLE
+	#define  TXE_UMA_ENABLE		UPD_ENABLE
 
 	/* Memory down data */
 	uint8_t  EnableMemoryDown;
-	#define  MEMORY_DOWN_DEFAULT            0
-	#define  MEMORY_DOWN_DISABLE            1
-	#define  MEMORY_DOWN_ENABLE             2
+	#define  MEMORY_DOWN_DEFAULT	UPD_DEFAULT
+	#define  MEMORY_DOWN_DISABLE	UPD_DISABLE
+	#define  MEMORY_DOWN_ENABLE	UPD_ENABLE
 
+	/*
+	 * PcdDRAMSpeed
+	 * Selection 0x0 , "800 MHz"
+	 * Selection 0x1 , "1066 MHz"
+	 * Selection 0x2 , "1333 MHz"
+	 * Selection 0x3 , "1600 MHz"
+	 */
 	uint8_t  DRAMSpeed;
-	#define  DRAM_SPEED_DEFAULT             0
-	#define  DRAM_SPEED_800MHZ              1
-	#define  DRAM_SPEED_1066MHZ             2
-	#define  DRAM_SPEED_1333MHZ             3
-	#define  DRAM_SPEED_1600MHZ             4
+	#define  DRAM_SPEED_DEFAULT	UPD_DEFAULT
+	#define  DRAM_SPEED_800MHZ	INCREMENT_FOR_DEFAULT(0)
+	#define  DRAM_SPEED_1066MHZ	INCREMENT_FOR_DEFAULT(1)
+	#define  DRAM_SPEED_1333MHZ	INCREMENT_FOR_DEFAULT(2)
+	#define  DRAM_SPEED_1600MHZ	INCREMENT_FOR_DEFAULT(3)
 
+	/*
+	 * PcdDRAMType
+	 * Selection 0x0 , "DDR3"
+	 * Selection 0x1 , "DDR3L"
+	 * Selection 0x2 , "DDR3U"
+	 * Selection 0x4 , "LPDDR2"
+	 * Selection 0x5 , "LPDDR3"
+	 * Selection 0x6 , "DDR4"
+	 */
 	uint8_t  DRAMType;
-	#define  DRAM_TYPE_DEFAULT              0
-	#define  DRAM_TYPE_DDR3                 1
-	#define  DRAM_TYPE_DDR3L                2
+	#define  DRAM_TYPE_DEFAULT	UPD_DEFAULT
+	#define  DRAM_TYPE_DDR3		INCREMENT_FOR_DEFAULT(0)
+	#define  DRAM_TYPE_DDR3L	INCREMENT_FOR_DEFAULT(1)
 
 	uint8_t  DIMM0Enable;
-	#define  DIMM0_ENABLE_DEFAULT           0
-	#define  DIMM0_DISABLE                  1
-	#define  DIMM0_ENABLE                   2
+	#define  DIMM0_ENABLE_DEFAULT	UPD_DEFAULT
+	#define  DIMM0_DISABLE		UPD_DISABLE
+	#define  DIMM0_ENABLE		UPD_ENABLE
 
 	uint8_t  DIMM1Enable;
-	#define  DIMM1_ENABLE_DEFAULT           0
-	#define  DIMM1_DISABLE                  1
-	#define  DIMM1_ENABLE                   2
+	#define  DIMM1_ENABLE_DEFAULT	UPD_DEFAULT
+	#define  DIMM1_DISABLE		UPD_DISABLE
+	#define  DIMM1_ENABLE		UPD_ENABLE
 
+	/*
+	 * PcdDIMMDWidth
+	 * Selection 0x0 , "x8"
+	 * Selection 0x1 , "x16"
+	 * Selection 0x2 , "x32"
+	 */
 	uint8_t  DIMMDWidth;
-	#define  DIMM_DWIDTH_DEFAULT            0
-	#define  DIMM_DWIDTH_X8                 1
-	#define  DIMM_DWIDTH_X16                2
-	#define  DIMM_DWIDTH_X32                3
+	#define  DIMM_DWIDTH_DEFAULT	UPD_DEFAULT
+	#define  DIMM_DWIDTH_X8		INCREMENT_FOR_DEFAULT(0)
+	#define  DIMM_DWIDTH_X16	INCREMENT_FOR_DEFAULT(1)
+	#define  DIMM_DWIDTH_X32	INCREMENT_FOR_DEFAULT(2)
 
+	/*
+	 * PcdDIMMDensity
+	 * Selection 0x0 , "1 Gbit"
+	 * Selection 0x1 , "2 Gbit"
+	 * Selection 0x2 , "4 Gbit"
+	 * Selection 0x3 , "8 Gbit"
+	 */
 	uint8_t  DIMMDensity;
-	#define  DIMM_DENSITY_DEFAULT           0
-	#define  DIMM_DENSITY_1G_BIT            1
-	#define  DIMM_DENSITY_2G_BIT            2
-	#define  DIMM_DENSITY_4G_BIT            3
-	#define  DIMM_DENSITY_8G_BIT            4
+	#define  DIMM_DENSITY_DEFAULT	UPD_DEFAULT
+	#define  DIMM_DENSITY_1G_BIT	INCREMENT_FOR_DEFAULT(0)
+	#define  DIMM_DENSITY_2G_BIT	INCREMENT_FOR_DEFAULT(1)
+	#define  DIMM_DENSITY_4G_BIT	INCREMENT_FOR_DEFAULT(2)
+	#define  DIMM_DENSITY_8G_BIT	INCREMENT_FOR_DEFAULT(3)
 
+	/*
+	 * PcdDIMMBusWidth
+	 * Selection 0x0 , "8 bits"
+	 * Selection 0x1 , "16 bits"
+	 * Selection 0x2 , "32 bits"
+	 * Selection 0x3 , "64 bits"
+	 */
 	uint8_t  DIMMBusWidth;
-	#define  DIMM_BUS_WIDTH_DEFAULT         0
-	#define  DIMM_BUS_WIDTH_8BIT            1
-	#define  DIMM_BUS_WIDTH_16BIT           2
-	#define  DIMM_BUS_WIDTH_32BIT           3
-	#define  DIMM_BUS_WIDTH_64BIT           4
+	#define  DIMM_BUS_WIDTH_DEFAULT	UPD_DEFAULT
+	#define  DIMM_BUS_WIDTH_8BIT	INCREMENT_FOR_DEFAULT(0)
+	#define  DIMM_BUS_WIDTH_16BIT	INCREMENT_FOR_DEFAULT(1)
+	#define  DIMM_BUS_WIDTH_32BIT	INCREMENT_FOR_DEFAULT(2)
+	#define  DIMM_BUS_WIDTH_64BIT	INCREMENT_FOR_DEFAULT(3)
 
+	/*
+	 * PcdDIMMSides
+	 * Selection 0x0 , "1 Ranks"
+	 * Selection 0x1 , "2 Ranks"
+	 */
 	uint8_t  DIMMSides;
-	#define  DIMM_SIDES_DEFAULT             0
-	#define  DIMM_SIDES_1RANK               1
-	#define  DIMM_SIDES_2RANK               2
+	#define  DIMM_SIDES_DEFAULT	UPD_DEFAULT
+	#define  DIMM_SIDES_1RANK	INCREMENT_FOR_DEFAULT(0)
+	#define  DIMM_SIDES_2RANK	INCREMENT_FOR_DEFAULT(1)
 
 	uint8_t  DIMMtCL;
-	#define  DIMM_TCL_DEFAULT               0
+	#define  DIMM_TCL_DEFAULT	UPD_DEFAULT
 
 	uint8_t  DIMMtRPtRCD;
-	#define  DIMM_TRP_TRCD_DEFAULT          0
+	#define  DIMM_TRP_TRCD_DEFAULT	UPD_DEFAULT
 
 	uint8_t  DIMMtWR;
-	#define  DIMM_TWR_DEFAULT               0
+	#define  DIMM_TWR_DEFAULT	UPD_DEFAULT
 
 	uint8_t  DIMMtWTR;
-	#define  DIMM_TWTR_DEFAULT              0
+	#define  DIMM_TWTR_DEFAULT	UPD_DEFAULT
 
 	uint8_t  DIMMtRRD;
-	#define  DIMM_TRRD_DEFAULT              0
+	#define  DIMM_TRRD_DEFAULT	UPD_DEFAULT
 
 	uint8_t  DIMMtRTP;
-	#define  DIMM_TRTP_DEFAULT              0
+	#define  DIMM_TRTP_DEFAULT	UPD_DEFAULT
 
 	uint8_t  DIMMtFAW;
-	#define  DIMM_TFAW_DEFAULT              0
+	#define  DIMM_TFAW_DEFAULT	UPD_DEFAULT
 
 /* ***** ACPI configuration ***** */
 	/* Options for these are in src/arch/x86/include/arch/acpi.h */
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 45b4154492..c69076cb6d 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -95,38 +95,33 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
 		UpdData->PcdMrcInitSPDAddr2 = config->PcdMrcInitSPDAddr2;
 	printk(BIOS_DEBUG, "SPD Addr2:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr2);
 
-	if (config->PcdSataMode != SATA_MODE_DEFAULT)
-		UpdData->PcdSataMode = config->PcdSataMode - SATA_MODE_IDE;
+	UPD_DEFAULT_CHECK(PcdSataMode);
+	UPD_DEFAULT_CHECK(PcdLpssSioEnablePciMode);
+	UPD_DEFAULT_CHECK(PcdMrcInitMmioSize);
+	UPD_DEFAULT_CHECK(PcdIgdDvmt50PreAlloc);
+	UPD_DEFAULT_CHECK(PcdApertureSize);
+	UPD_DEFAULT_CHECK(PcdGttSize);
+	UPD_DEFAULT_CHECK(SerialDebugPortAddress);
+	UPD_DEFAULT_CHECK(SerialDebugPortType);
+	UPD_DEFAULT_CHECK(PcdMrcDebugMsg);
+	UPD_DEFAULT_CHECK(PcdSccEnablePciMode);
+	UPD_DEFAULT_CHECK(IgdRenderStandby);
+	UPD_DEFAULT_CHECK(TxeUmaEnable);
 
 	if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) ||
 			(config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE))
 		UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode;
 
-	if (config->PcdLpssSioEnablePciMode != LPSS_PCI_MODE_DEFAULT)
-		UpdData->PcdLpssSioEnablePciMode = config->PcdLpssSioEnablePciMode -
-		LPSS_PCI_MODE_DISABLE;
-
 	if (config->PcdMrcInitTsegSize != TSEG_SIZE_DEFAULT)
-		UpdData->PcdMrcInitTsegSize = config->PcdMrcInitTsegSize;
-	printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize);
-
-	if (config->PcdMrcInitMmioSize != MMIO_SIZE_DEFAULT)
-		UpdData->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
-	printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize);
+		UpdData->PcdMrcInitTsegSize = config->PcdMrcInitTsegSize - 1;
 
-	if (config->PcdIgdDvmt50PreAlloc != IGD_MEMSIZE_DEFAULT)
-		UpdData->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc;
-	printk(BIOS_DEBUG, "IGD Memory Size:\t%d MB\n",
-		UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER);
-
-	if (config->PcdApertureSize != APERTURE_SIZE_DEFAULT)
-		UpdData->PcdApertureSize = config->PcdApertureSize;
+	printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize);
+	printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize);
 	printk(BIOS_DEBUG, "Aperture Size:\t\t%d MB\n",
 		APERTURE_SIZE_BASE << UpdData->PcdApertureSize);
-
-	if (config->PcdGttSize != GTT_SIZE_DEFAULT)
-		UpdData->PcdGttSize = config->PcdGttSize;
-	printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize);
+	printk(BIOS_DEBUG, "IGD Memory Size:\t%d MB\n",
+		UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER);
+	printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize);
 
 	/* Advance dev to PCI device 0.0 */
 	for (dev = &dev_root; dev; dev = dev_find_next_pci_device(dev)){
@@ -312,33 +307,6 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
 	printk(BIOS_DEBUG, "Xhci:\t\t\t%s\n",
 		UpdData->PcdEnableXhci?"Enabled":"Disabled");
 
-	if (config->SerialDebugPortAddress != SerialDebugPortAddress_DEFAULT) {
-		UpdData->SerialDebugPortAddress = config->SerialDebugPortAddress;
-	}
-	if (config->SerialDebugPortType != SERIAL_DEBUG_PORT_DEFAULT) {
-		UpdData->SerialDebugPortType
-			= config->SerialDebugPortType - SERIAL_DEBUG_PORT_TYPE_NONE;
-	}
-	if (config->PcdMrcDebugMsg != MRC_DEBUG_MSG_DEFAULT) {
-		UpdData->PcdMrcDebugMsg
-			= config->PcdMrcDebugMsg - MRC_DEBUG_MSG_DISABLE;
-		printk (BIOS_DEBUG, "MRC Debug Message:\t%s\n",
-			(UpdData->PcdMrcDebugMsg) ? "Enabled" : "Disabled");
-	}
-	if (config->PcdSccEnablePciMode != SCC_PCI_MODE_DEFAULT) {
-		UpdData->PcdSccEnablePciMode
-			= config->PcdSccEnablePciMode - SCC_PCI_MODE_DISABLE;
-	}
-	if (config->IgdRenderStandby != IGD_RENDER_STANDBY_DEFAULT) {
-		UpdData->IgdRenderStandby
-			= config->IgdRenderStandby - IGD_RENDER_STANDBY_DISABLE;
-		printk (BIOS_DEBUG, "IGD Render Standby:\t%s\n",
-			(UpdData->IgdRenderStandby) ? "Enabled" : "Disabled");
-	}
-	if (config->TxeUmaEnable != TXE_UMA_DEFAULT) {
-		UpdData->TxeUmaEnable = config->TxeUmaEnable - TXE_UMA_DISABLE;
-	}
-
 	/* set memory down parameters */
 	if (config->EnableMemoryDown != MEMORY_DOWN_DEFAULT) {
 		UpdData->PcdMemoryParameters.EnableMemoryDown