diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-04 15:14:29 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-03-16 09:01:50 +0000 |
| commit | 5926ae24a6fa4ebf83f24281c3df88b61076b838 (patch) | |
| tree | bb64e20821959f34603fd5bd72502d6da4dd18dd /src/soc/intel/fsp_baytrail | |
| parent | 0e3f7d47804d39912faec5a56bc9cddf91ea354b (diff) | |
drivers/intel/fsp1_0: Deduplicate code
Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0.
Allows to have a common entry after FSP-M.
Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 12 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/romstage.h | 1 |
2 files changed, 0 insertions, 13 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c9cbcfe960..7e90142250 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -336,16 +336,4 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } -/* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, - VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; - - if (Status == 0xFFFFFFFF) { - system_reset(); - } - romstage_main_continue(Status, HobListPtr); -} - #endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 9cbc95c240..5f0bd8d9c3 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -27,7 +27,6 @@ void report_platform_info(void); #include <drivers/intel/fsp1_0/fsp_util.h> void main(FSP_INFO_HEADER *fsp_info_header); -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 |