fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 84 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c
new file mode 100644
index 0000000000..b74e41ea31
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/tsc_freq.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <baytrail/msr.h>
+#if !defined(__PRE_RAM__)
+#include <baytrail/ramstage.h>
+#else
+#include <baytrail/romstage.h>
+#endif
+
+unsigned bus_freq_khz(void)
+{
+	msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+	switch (clk_info.lo & 0x3) {
+	case 0:
+		return 83333;
+	case 1:
+		return 100000;
+	case 2:
+		return 133333;
+	case 3:
+		return 116666;
+	default:
+		return 0;
+	}
+}
+
+unsigned long tsc_freq_mhz(void)
+{
+	msr_t platform_info;
+	unsigned bclk_khz = bus_freq_khz();
+
+	if (!bclk_khz)
+		return 0;
+
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
+}
+
+#if !defined(__SMM__)
+
+void set_max_freq(void)
+{
+	msr_t perf_ctl;
+	msr_t msr;
+
+	/* Enable speed step. */
+	msr = rdmsr(MSR_IA32_MISC_ENABLES);
+	msr.lo |= (1 << 16);
+	wrmsr(MSR_IA32_MISC_ENABLES, msr);
+
+	/* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
+	* the PERF_CTL. */
+	msr = rdmsr(MSR_IACORE_RATIOS);
+	perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
+	/* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
+	* the PERF_CTL. */
+	msr = rdmsr(MSR_IACORE_VIDS);
+	perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
+	perf_ctl.hi = 0;
+
+	wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
+}
+
+#endif /* __SMM__ */