diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/fsp_baytrail/southcluster.c | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/southcluster.c')
-rw-r--r-- | src/soc/intel/fsp_baytrail/southcluster.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 8fce928a2d..e6947b4d6d 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -139,7 +139,7 @@ static void sc_enable_serial_irqs(struct device *dev) write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) /* * SoC requires that the System BIOS first set the SERIRQ logic to * continuous mode operation for at least one frame before switching |