diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-14 05:41:41 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-15 06:55:59 +0000 |
| commit | faf20d30a6e451d45e29613e3f4603dc72771843 (patch) | |
| tree | d1c3df6e87473d66633fb3a4a8cec736fdda2cd7 /src/soc/intel/fsp_baytrail/smm.c | |
| parent | f091f4daf7e76cff3cdf9b7a19bb77281fb6af9d (diff) | |
soc/intel: Rename some SMM support functions
Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.
Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/smm.c')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/smm.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index df55433314..0c40429aae 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -20,21 +20,22 @@ #include <arch/io.h> #include <device/mmio.h> #include <cpu/x86/smm.h> +#include <cpu/intel/smm_reloc.h> #include <bootstate.h> +#include <soc/gpio.h> #include <soc/iomap.h> #include <soc/pmc.h> -#include <soc/smm.h> /* Save the gpio route register. The settings are committed from - * southcluster_smm_enable_smi(). */ + * smm_southbridge_enable_smi(). */ static uint32_t gpio_route; -void southcluster_smm_save_gpio_route(uint32_t route) +void smm_southcluster_save_gpio_route(uint32_t route) { gpio_route = route; } -void southcluster_smm_clear_state(void) +void smm_southbridge_clear_state(void) { uint32_t smi_en; @@ -59,7 +60,7 @@ void southcluster_smm_clear_state(void) clear_pmc_status(); } -static void southcluster_smm_route_gpios(void) +static void smm_southcluster_route_gpios(void) { u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; @@ -84,7 +85,7 @@ static void southcluster_smm_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void southcluster_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); @@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void) disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ - southcluster_smm_route_gpios(); + smm_southcluster_route_gpios(); /* Enable SMI generation: * - on APMC writes (io 0xb2) |