diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:22:01 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:33:03 +0200 |
| commit | 15e439a72e26b72394b14e3777541819468bc10c (patch) | |
| tree | 0b70bf36407656572248332e647b33636d0ca66f /src/soc/intel/fsp_baytrail/fsp | |
| parent | 9e6d143a82a852ddfa64f20ceb8695939c1dace1 (diff) | |
soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/fsp')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 107bfad569..fb179e65dc 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -304,7 +304,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif - if (prev_sleep_state == 3) { + if (prev_sleep_state == ACPI_S3) { /* S3 resume */ if ( pFspInitParams->NvsBufferPtr == NULL) { /* If waking from S3 and no cache then. */ |