diff options
| author | York Yang <york.yang@intel.com> | 2014-11-04 17:04:37 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-11-21 23:05:19 +0100 |
| commit | fc1c1b572f3523950cdf5cbf0c2967365700cfc3 (patch) | |
| tree | 2e84f2d2f0a76f005bd2d369b390ca9e88982137 /src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | |
| parent | 3fb8b0d75b2a40a1e81e10b6abe9f63c71f9066c (diff) | |
intel/fsp_baytrail: add Gold3 FSP support
Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION
making platform more configurable via devicetree.cb
Update the UPD_DATA_REGION structure and pass settings to FSP
Add Baytrail Gold2 and earlier FSP backward compatible, as Gold3
FSP changes UPD_DATA_REGION struct
Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/7334
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h')
| -rwxr-xr-x[-rw-r--r--] | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 1b603986ea..6df14845d8 100644..100755 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -46,4 +47,7 @@ #define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */ #define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */ +/* Revision of the FSP binary */ +#define FSP_GOLD3_REV_ID 0x00000303 + #endif /* CHIPSET_FSP_UTIL_H */ |