diff options
| author | Ben Gardner <gardner.ben@gmail.com> | 2016-03-11 15:20:32 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-13 03:07:16 +0100 |
| commit | cbfec89037ba999ac2377fc82054e14125b9b08c (patch) | |
| tree | a3bb1e769eaa47d72b37eda4c82d250dabf0d0a4 /src/soc/intel/fsp_baytrail/chip.h | |
| parent | 983608daa5b75538c1e11cfad67d5badff73dafa (diff) | |
intel/fsp_baytrail: Fix LPE initialization and enable ACPI mode
This change properly assigns resources to the LPE (Low Power Engine for
Audio) and enables ACPI mode.
lpe.c was copied from intel/baytrail with a few minor adjustment for the
different config structure.
ACPI mode requires setting LpeAcpiModeEnable=LPE_ACPI_MODE_ENABLED and
applying the patch that disables clearing gnvs.
https://review.coreboot.org/#/c/14040/
Change-Id: I3fff9aa158bde88e571082642d4f985a5ae1976e
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/chip.h')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/chip.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h index 35dafa9af1..156a08434c 100644 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -342,6 +342,10 @@ struct soc_intel_fsp_baytrail_config { uint8_t DIMMtFAW; #define DIMM_TFAW_DEFAULT UPD_DEFAULT + /* LPE Audio Clock configuration. */ + int lpe_codec_clk_freq; /* 19 or 25 are valid. */ + int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + /* ***** ACPI configuration ***** */ /* Options for these are in src/arch/x86/include/arch/acpi.h */ uint8_t fadt_pm_profile; |