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authorMartin Roth <gaumless@gmail.com>2015-02-12 22:51:57 -0700
committerMartin Roth <gaumless@gmail.com>2015-03-12 20:35:49 +0100
commitd08057aa20d8dff404ba9121a5d2052ae6575356 (patch)
tree72c3bd33b2ad4645916b70a7fac9d3d730de256c /src/soc/intel/fsp_baytrail/baytrail
parent48b3dbc7483f5404a2dfb3b8bb5f4bcf7d3c4b09 (diff)
intel/fsp_baytrail: Add PCI Root Port IRQ Routing
This change generates the ASL tables needed for the PCIe bridge routing. It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } } Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/baytrail')
-rw-r--r--src/soc/intel/fsp_baytrail/baytrail/irq.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/irq.h b/src/soc/intel/fsp_baytrail/baytrail/irq.h
index 98ca116c57..6f56b1ffd9 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/irq.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/irq.h
@@ -160,6 +160,9 @@ extern const struct baytrail_irq_route global_baytrail_irq_route;
#define PIRQ_PIC(pirq_, pic_irq_) \
[PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
+/* used for ACPI only */
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_)
+
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
#endif /* _BAYTRAIL_IRQ_H_ */