diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/soc/intel/fsp_baytrail/baytrail | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/fsp_baytrail/baytrail')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/gpio.h | 16 |
2 files changed, 12 insertions, 9 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h index d3a23770dd..1982c278d1 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -34,8 +34,11 @@ /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_IBASE 0xfed08000 #define DEFAULT_PBASE 0xfed03000 +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 - +#endif /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index a45254a8af..e06c8d6bee 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -353,20 +353,20 @@ void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); #define PCU_SMB_CLK_PAD 88 #define PCU_SMB_DATA_PAD 90 -static inline unsigned int score_pconf0(int pad_num) +static inline uint32_t *score_pconf0(int pad_num) { - return GPSCORE_PAD_BASE + pad_num * 16; + return (uint32_t *)(GPSCORE_PAD_BASE + pad_num * 16); } -static inline unsigned int ssus_pconf0(int pad_num) +static inline uint32_t *ssus_pconf0(int pad_num) { - return GPSSUS_PAD_BASE + pad_num * 16; + return (uint32_t *)(GPSSUS_PAD_BASE + pad_num * 16); } static inline void score_select_func(int pad, int func) { uint32_t reg; - uint32_t pconf0_addr = score_pconf0(pad); + uint32_t *pconf0_addr = score_pconf0(pad); reg = read32(pconf0_addr); reg &= ~0x7; @@ -377,7 +377,7 @@ static inline void score_select_func(int pad, int func) static inline void ssus_select_func(int pad, int func) { uint32_t reg; - uint32_t pconf0_addr = ssus_pconf0(pad); + uint32_t *pconf0_addr = ssus_pconf0(pad); reg = read32(pconf0_addr); reg &= ~0x7; @@ -390,14 +390,14 @@ static inline void ssus_select_func(int pad, int func) /* These functions require that the input pad be configured as an input GPIO */ static inline int score_get_gpio(int pad) { - uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG; + uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); return read32(val_addr) & PAD_VAL_HIGH; } static inline int ssus_get_gpio(int pad) { - uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG; + uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); return read32(val_addr) & PAD_VAL_HIGH; } |