fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 68 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_baytrail/baytrail/spi.h b/src/soc/intel/fsp_baytrail/baytrail/spi.h
new file mode 100644
index 0000000000..ee1648a135
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/baytrail/spi.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BAYTRAIL_SPI_H_
+#define _BAYTRAIL_SPI_H_
+
+#include <stdint.h>
+
+/* These registers live behind SPI_BASE_ADDRESS. */
+#define HSFSTS				0x04
+# define FLOCKDN			(0x1 << 15)
+#define PREOP				0x94
+#define OPTYPE				0x96
+#define OPMENU0				0x98
+#define OPMENU1				0x9c
+#define LVSCC				0xc4
+# define VCL				(0x1 << 23)
+# define EO(x)				(((x) & 0xff) << 8)
+# define WG_1_BYTE			(0x0 << 2)
+# define WG_64_BYTE			(0x1 << 2)
+# define BES_256_BYTE			(0x0 << 0)
+# define BES_4_KB			(0x1 << 0)
+# define BES_8_KB			(0x2 << 0)
+# define BES_64_KB			(0x3 << 0)
+#define UVSCC				0xc8
+#define SCS				0xf8
+# define SMIWPEN			(0x1 << 7)
+#define BCR				0xfc
+# define EISS				(0x1 << 5)
+# define SRC_MASK			(0x3 << 2)
+# define SRC_CACHE_NO_PREFETCH		(0x0 << 2)
+# define SRC_NO_CACHE_NO_PREFETCH	(0x1 << 2)
+# define SRC_CACHE_PREFETCH		(0x2 << 2)
+# define BCR_LE				(0x1 << 1)
+# define BCR_WPD			(0x1 << 0)
+
+/*
+ * SPI lockdown configuration.
+ */
+struct spi_config {
+	uint16_t preop;
+	uint16_t optype;
+	uint32_t opmenu[2];
+	uint32_t lvscc;
+	uint32_t uvscc;
+};
+
+/* Return 0 on success < 0 on failure. */
+int mainboard_get_spi_config(struct spi_config *cfg);
+
+#endif /* _BAYTRAIL_SPI_H_ */
+