intel/fsp_baytrail: rename include folder baytrail to include/soc

This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.

Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

1 files changed, 0 insertions, 31 deletions

diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h
deleted file mode 100644
index 5c2f98aa11..0000000000
--- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _BAYTRAIL_RAMSTAGE_H_
-#define _BAYTRAIL_RAMSTAGE_H_
-
-#include <device/device.h>
-
-/* The baytrail_init_pre_device() function is called prior to device
- * initialization, but it's after console and cbmem has been reinitialized. */
-void baytrail_init_pre_device(void);
-void baytrail_init_cpus(device_t dev);
-void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
-
-extern struct pci_operations soc_pci_ops;
-
-#endif /* _BAYTRAIL_RAMSTAGE_H_ */