fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 44 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_baytrail/baytrail/ehci.h b/src/soc/intel/fsp_baytrail/baytrail/ehci.h
new file mode 100644
index 0000000000..a1edd6dffe
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/baytrail/ehci.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BAYTRAIL_EHCI_H
+#define BAYTRAIL_EHCI_H
+
+/* EHCI PCI Registers */
+#define EHCI_CMD_STS		0x04
+# define  INTRDIS		  (1 << 10)
+#define EHCI_SBRN_FLA_PWC	0x60
+# define  PORTWKIMP		  (1 << 16)
+# define  PORTWKCAPMASK		  (0x3ff << 17)
+#define EHCI_USB2PDO		0x64
+
+/* EHCI Memory Registers */
+#define USB2CMD			0x20
+# define  USB2CMD_ASE		  (1 << 5)
+# define  USB2CMD_PSE		  (1 << 4)
+# define  USB2CMD_HCRESET	  (1 << 1)
+# define  USB2CMD_RS		  (1 << 0)
+#define USB2STS			0x24
+# define  USB2STS_HCHALT	  (1 << 12)
+
+/* RCBA EHCI Registers */
+#define RCBA_FUNC_DIS		0x220
+# define  RCBA_EHCI_DIS		  (1 << 0)
+
+#endif /* BAYTRAIL_EHCI_H */