diff options
| author | Ben Gardner <gardner.ben@gmail.com> | 2015-12-08 21:20:25 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-16 01:10:06 +0100 |
| commit | fa6014a6ec8253de8c86b0180221856a1398e70b (patch) | |
| tree | 55d71de574980b69930abed6bf3733050e6b69ac /src/soc/intel/fsp_baytrail/baytrail/baytrail.h | |
| parent | 1e1c7ac3b4cb6d85eb602e04b0e4da8c042846c0 (diff) | |
intel/fsp_baytrail: rename include folder baytrail to include/soc
This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.
Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/baytrail/baytrail.h')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 73 |
1 files changed, 0 insertions, 73 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h deleted file mode 100644 index bc75567ce0..0000000000 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ -#define __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ - -#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS -#define CPU_MICROCODE_CBFS_LEN 0x26000 - -/* Southbridge internal device IO BARs (Set to match FSP settings) */ -#define SMBUS_IO_BASE 0xefa0 -#define SMBUS_SLAVE_ADDR 0x24 -#define DEFAULT_GPIOBASE 0x0500 -#define DEFAULT_ABASE 0x0400 - -/* Southbridge internal device MEM BARs (Set to match FSP settings) */ -#define DEFAULT_IBASE 0xfed08000 -#define DEFAULT_PBASE 0xfed03000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ - -/* Device 0:0.0 PCI configuration space (Host Bridge) */ - -/* SOC types */ -#define SOC_TYPE_BAYTRAIL 0x0F1C - -#ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } - -#define SKPAD 0xFC - -int bridge_silicon_revision(void); -void rangeley_early_initialization(void); - -#ifndef __PRE_RAM__ -/* soc.c */ -int soc_silicon_revision(void); -int soc_silicon_type(void); -int soc_silicon_supported(int type, int rev); -void soc_enable(device_t dev); - -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); -void report_platform_info(void); - -#endif /* __PRE_RAM__ */ -#endif /* __ASSEMBLER__ */ - -#endif /* __ACPI__ */ -#endif |