diff options
| author | Christian Gmeiner <christian.gmeiner@gmail.com> | 2022-10-04 09:35:08 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-12 13:10:14 +0000 |
| commit | d8fd2deda1e66acd0a6162bbea1d8d1ff524f055 (patch) | |
| tree | bfe5b76816a3e2c542b65c21b5724fdb78b6458d /src/soc/intel/elkhartlake | |
| parent | 803241c03e4987d5039c2aa4babcf8b3718f559f (diff) | |
soc/intel/ehl: Support maximum memory frequency selection
Makes it possible to configure the maximum allowed/supported DDR memory
frequency on a per mainboard basis.
Test
- Define maximum memory frequency in mainboard devicetree.cb
- Boot into Linux and run 'sudo dmidecode --type 17' to check memory
speed
- Boot into Linux and run 'phoronix-test-suite benchmark ramspeed'
Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68097
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/elkhartlake')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/romstage/fsp_params.c | 6 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 68810f4a24..d63844ffe7 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -444,6 +444,16 @@ struct soc_intel_elkhartlake_config { bool PsePwmPinEn[16]; /* PSE Console Shell */ bool PseShellEn; + + /* + * DDR Frequency Limit + * + * Maximum Memory Frequency Selections in Mhz. + * Values: 1067, 1200, 1333, 1400, 1600, 1800, 1867, 2000, 2133, + * 2200, 2400, 2600, 2667, 2800, 2933, 3000, 3200, 3467, + * 3600, 3733, 4000, 4200, 4267 and 0 for Auto. + */ + uint16_t max_dram_speed_mts; }; typedef struct soc_intel_elkhartlake_config config_t; diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 5c8c995959..d2d118a793 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -123,6 +123,12 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, } /* PSE (Intel Programmable Services Engine) switch */ m_cfg->PchPseEnable = CONFIG(PSE_ENABLE) && cbfs_file_exists("pse.bin"); + + /* DDR Frequency Limit */ + if (config->max_dram_speed_mts) { + m_cfg->DdrFreqLimit = config->max_dram_speed_mts; + m_cfg->DdrSpeedControl = 1; + } } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |