soc/intel/ehl: Set Ethernet controller to D0 power state

To be able to change the MAC addresses, it is necessary that the
controllers are in D0 power state. As of FSP MR3, Intel has set the
controllers to D3 power state at the end of FSP-S TSN GbE
initialization. This patch sets the state back to D0 before the
programming of the MAC addresses.

Test:
- Build coreboot with FSP MR4 for mc_ehl2 mainboard
- Boot into Linux and check MAC addr via 'ip a'

Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c
index ea2ef0e5c7..49ce4da95b 100644
--- a/src/soc/intel/elkhartlake/tsn_gbe.c
+++ b/src/soc/intel/elkhartlake/tsn_gbe.c
@@ -3,6 +3,7 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <intelblocks/lpss.h>
 #include <soc/soc_chip.h>
 #include <soc/tsn_gbe.h>
 #include <timer.h>
@@ -99,6 +100,13 @@ static void tsn_set_phy2mac_irq_polarity(void *base, enum tsn_phy_irq_polarity p
 	}
 }
 
+static void gbe_tsn_enable(struct device *dev)
+{
+	/* Ensure controller is in D0 state. */
+	lpss_set_power_state(PCI_DEV(0, PCI_SLOT(dev->path.pci.devfn),
+			PCI_FUNC(dev->path.pci.devfn)), STATE_D0);
+}
+
 static void gbe_tsn_init(struct device *dev)
 {
 	/* Get the base address of the I/O registers in memory space */
@@ -127,6 +135,7 @@ static struct device_operations gbe_tsn_ops  = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
+	.enable           = gbe_tsn_enable,
 	.init             = gbe_tsn_init,
 };