diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 12:39:22 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-01 12:14:02 +0000 |
| commit | c7cfe0ba54bd280b8c4a5079bb2f6e19334f6dea (patch) | |
| tree | a7a769621549d3de3e8dd371544c74baee07bd38 /src/soc/intel/elkhartlake | |
| parent | 3657187789ee72834539b82cac6dda525421e4ed (diff) | |
soc/intel: Refactor `xdci_can_enable()` function
The same pattern appears on all `xdci_can_enable()` call sites. Move the
logic inside the function and take the xDCI devfn as parameter.
Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/elkhartlake')
| -rw-r--r-- | src/soc/intel/elkhartlake/fsp_params.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index e738d1125a..210040e75b 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -181,10 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->UsbClockGatingEnable = 1; params->UsbPowerGatingEnable = 1; - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); /* PCIe root ports config */ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |