summaryrefslogtreecommitdiff
path: root/src/soc/intel/elkhartlake/uart.c
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2023-03-04 03:33:54 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-09 22:52:38 +0000
commit649426539b73e4ada1eb0631bfa3b02be75dfd02 (patch)
treef3bd07921d19c6e6ec2b9506e3fd9ff704df5822 /src/soc/intel/elkhartlake/uart.c
parentbd9dd420d7e0e5c2acb4073c0f4b3faec4d31ec8 (diff)
soc/amd/common/cpu/Kconfig: use Cxxx as CPU string for all non-CAR SoCs
Picasso already uses the Cxxx ACPI CPU device naming scheme, due to it being what the AGESA reference code uses. We initially relied on the AGESA/FSP generated SSDT for the P- and C-state support before we had a native implementation for this in coreboot. The Cxxx naming scheme can also be used for the other AMD SoCs except Stoneyridge which is pre-Zen and doesn't select SOC_AMD_COMMON_BLOCK_NONCAR. The main advantage of using Cxxx instead of CPxx is that the Cxxx scheme supports systems with more than 256 CPU threads. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I884f5c0f234b5a3942dacd60847b2f095f9c0704 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73620 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake/uart.c')
0 files changed, 0 insertions, 0 deletions