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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-04-28 09:13:21 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-30 23:21:11 +0000 |
| commit | 2263e9b8817235223a56a99681b114f640dfc491 (patch) | |
| tree | c245045af288dd1f0930f9084df0f6a04d2a4df1 /src/soc/intel/elkhartlake/spi.c | |
| parent | 5e1c9a9fd6266fa8b04199535e1fbecc84292cda (diff) | |
drivers/i2c/designware: Use safe defaults for SCL parameters
Inspired by discussion in CB:22822.
If I2C bus step response has not been measured, assume the layout to
have been designed with a minimal capacitance and SCL rise and fall
times of 0 ns. The calculations will add the required amount of
reference clocks for the host to drive SCL high or low, such that the
maximum bus frequency specification is met.
Change-Id: Icbafae22c83ffbc16c179fb5412fb4fd6b70813a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52723
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake/spi.c')
0 files changed, 0 insertions, 0 deletions