soc/intel/elkhartlake: Do initial SoC commit till ramstage

Clone entirely from Jasperlake

List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jsp" with "mcc"
4. Rename structure based on Jasperlake with Elkhartlake
5. Clean up upd override in fsp_params.c will be added later
6. Sort #include files alphabetically as per comment
7. Remove doc details from espi.c until it is ready
8. Remove pch_isclk & camera clocks related codes
9. Add new #define NMI_STS_CNT & NMI_EN as per comment

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/soc/intel/elkhartlake/p2sb.c b/src/soc/intel/elkhartlake/p2sb.c
new file mode 100644
index 0000000000..0ddd007920
--- /dev/null
+++ b/src/soc/intel/elkhartlake/p2sb.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <intelblocks/p2sb.h>
+
+void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
+{
+	uint32_t mask;
+
+	if (count != P2SB_EP_MASK_MAX_REG) {
+		printk(BIOS_ERR, "Unable to program EPMASK registers\n");
+		return;
+	}
+
+	/* Remove the host accessing right to PSF register range.
+	 * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable sideband
+	 * access for PCI Root Bridge.
+	 */
+	mask = (1 << 29) | (1 << 28) | (1 << 27)  | (1 << 26);
+
+	ep_mask[P2SB_EP_MASK_5_REG] = mask;
+
+	/*
+	 * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband
+	 * access for Broadcast and Multicast.
+	 */
+	mask = (1 << 31) | (1 << 30);
+
+	ep_mask[P2SB_EP_MASK_7_REG] = mask;
+}