diff options
| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | 2020-11-27 05:33:08 -0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2020-12-10 10:49:15 +0000 |
| commit | 344f68be108fca3b9fe8e4280ce8015f1dd8c8e1 (patch) | |
| tree | 79cc2534dcd092eec085a93e91f9fd51f594d3df /src/soc/intel/elkhartlake/meminit.c | |
| parent | ed42c7ef515edb1a017b837f8e6d26b801e8d2df (diff) | |
mb/intel/ehlcrb: Add EHL CRB memory initialization support
Update memory parameters based on memory type supported by
Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
initialization
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/meminit.c')
| -rw-r--r-- | src/soc/intel/elkhartlake/meminit.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/elkhartlake/meminit.c b/src/soc/intel/elkhartlake/meminit.c index cd777ba3a0..f1f82708d8 100644 --- a/src/soc/intel/elkhartlake/meminit.c +++ b/src/soc/intel/elkhartlake/meminit.c @@ -109,6 +109,7 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, /* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; - + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; + mem_cfg->CaVrefConfig = board_cfg->vref_ca_config; mem_cfg->UserBd = board_cfg->UserBd; } |