mb/intel/ehlcrb: Add EHL CRB memory initialization support

Update memory parameters based on memory type supported by
Elkhart Lake CRB:

1. Update spd data for EHL LPDDR4X memory
   - DQ byte map
   - DQS CPU-DRAM map
   - Rcomp resistor
   - Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
   initialization

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/src/soc/intel/elkhartlake/meminit.c b/src/soc/intel/elkhartlake/meminit.c
index cd777ba3a0..f1f82708d8 100644
--- a/src/soc/intel/elkhartlake/meminit.c
+++ b/src/soc/intel/elkhartlake/meminit.c
@@ -109,6 +109,7 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
 
 	/* Early Command Training Enabled */
 	mem_cfg->ECT = board_cfg->ect;
-
+	mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved;
+	mem_cfg->CaVrefConfig = board_cfg->vref_ca_config;
 	mem_cfg->UserBd = board_cfg->UserBd;
 }