mb/intel/ehlcrb: Add EHL CRB memory initialization support

Update memory parameters based on memory type supported by
Elkhart Lake CRB:

1. Update spd data for EHL LPDDR4X memory
   - DQ byte map
   - DQS CPU-DRAM map
   - Rcomp resistor
   - Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
   initialization

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 16 insertions, 1 deletions

diff --git a/src/soc/intel/elkhartlake/include/soc/meminit.h b/src/soc/intel/elkhartlake/include/soc/meminit.h
index ea4664a150..2dcbd13253 100644
--- a/src/soc/intel/elkhartlake/include/soc/meminit.h
+++ b/src/soc/intel/elkhartlake/include/soc/meminit.h
@@ -88,11 +88,26 @@ struct mb_cfg {
 
 	/*
 	 * Rcomp target values.  These will typically be the following
-	 * values for Elkhart Lake : { 80, 40, 40, 40, 30 }
+	 * values for Elkhart Lake : { 60, 40, 30, 20, 30 }
 	 */
 	uint16_t rcomp_targets[5];
 
 	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	uint8_t dq_pins_interleaved;
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	uint8_t vref_ca_config;
+
+	/*
 	 * Early Command Training Enable/Disable Control
 	 * 1 = enable, 0 = disable
 	 */