diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-05-16 16:21:51 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-17 21:08:47 +0000 |
| commit | da541327d2ecfc9043205a7bd81c0ed71c4313fa (patch) | |
| tree | f8f915a71c748ab9e871a122340ad6ddf4109ae5 /src/soc/intel/elkhartlake/chip.h | |
| parent | 46af7f7442f53939130ed2eda2c00bb72cfa7746 (diff) | |
soc/intel/elkhartlake: Enable SMBus depending on dev state
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's
state in the devicetree. This avoids having to manually make sure the
SMBus PCI device and the `SmbusEnable` setting are in sync.
Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake/chip.h')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 3e1d56e17e..8764657b19 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -227,9 +227,6 @@ struct soc_intel_elkhartlake_config { /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; uint8_t ScsEmmcDdr50Enabled; |