diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-03-17 09:58:56 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-21 11:18:11 +0000 |
| commit | fd4f8911c12cb28467054eb06896bae1e0337df0 (patch) | |
| tree | b3d7dc70aa8448a6d76f4c10f1686be5edaadbca /src/soc/intel/elkhartlake/chip.h | |
| parent | 1af4b289f06b6f8b9eb14b4754bedd3fbce944bf (diff) | |
soc/intel/elkhartlake: Make PCIe root port speed limit configurable
In cases where there are limitations on the connected device behind the
PCIe root port it can be necessary to limit the speed. The FSP parameter
'PcieRpPcieSpeed' allows to set the speed limit.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/chip.h')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index b15d78a1ee..e8505f4a37 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -239,6 +239,9 @@ struct soc_intel_elkhartlake_config { /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + /* PCIe root port speed. 0: Auto (Default); 1: Gen1; 2: Gen2; 3: Gen3 */ + uint8_t PcieRpPcieSpeed[CONFIG_MAX_ROOT_PORTS]; + /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; uint8_t ScsEmmcDdr50Enabled; |