diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-04-27 11:24:05 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-21 17:40:52 +0000 |
| commit | dccdaceb494fdb0466a1c46b68df3642280f587f (patch) | |
| tree | f9fde441a368a3a17c40720865bcc5ba9f3c9e7d /src/soc/intel/elkhartlake/chip.h | |
| parent | 8698a6f5a9d656c165f594cb9cd532a80d8e5e99 (diff) | |
soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY. The inverting can be activated via
devicetree parameter.
Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/chip.h')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 618d00f2e8..68810f4a24 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -56,6 +56,12 @@ enum tsn_phy_type { SGMII_plus = 3, }; +/* TSN GBE PHY-to-MAC IRQ polarity: 0: falling edge, 1: rising edge */ +enum tsn_phy_irq_polarity { + FALLING_EDGE, + RISING_EDGE, +}; + /* * PSE native pins and ownership assignment:- * 0: Disable/pins are not owned by PSE/host @@ -395,6 +401,8 @@ struct soc_intel_elkhartlake_config { bool PseTsnGbeMultiVcEnable[MAX_PSE_TSN_PORTS]; /* PSE TSN Phy Interface Type */ enum tsn_phy_type PseTsnGbePhyType[MAX_PSE_TSN_PORTS]; + enum tsn_phy_irq_polarity pch_tsn_phy_irq_edge; + enum tsn_phy_irq_polarity pse_tsn_phy_irq_edge[MAX_PSE_TSN_PORTS]; /* PSE related */ /* |