diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-07-27 04:28:20 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 16:09:56 +0000 |
| commit | 7760fe4645c55c2025a4fc9de0b205b8fd7031d3 (patch) | |
| tree | 51f0641da6621b6d46a2acbcad78060af144ae29 /src/soc/intel/elkhartlake/acpi | |
| parent | 5cd7579ee54dbd9d424c6adc4b0228bcede95ffb (diff) | |
soc/intel/elkhartlake: Add PSE TSN support
Enable PSE GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Add PSE GBE ACPI devices
3. Refactor PCH GBE FSP-S code and merge it together
with PSE GBE code
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/acpi')
| -rw-r--r-- | src/soc/intel/elkhartlake/acpi/tsn_glan.asl | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/acpi/tsn_glan.asl b/src/soc/intel/elkhartlake/acpi/tsn_glan.asl index de4f0b66a4..eb5fed89fe 100644 --- a/src/soc/intel/elkhartlake/acpi/tsn_glan.asl +++ b/src/soc/intel/elkhartlake/acpi/tsn_glan.asl @@ -13,3 +13,31 @@ Device(GTSN) { TADH, 32, } } + +/* Intel PSE TSN Ethernet Controller #1 0:1d.1 */ + +Device(OTN0) { + Name(_ADR, 0x001D0001) + OperationRegion(TSRT,PCI_Config,0x00,0x100) + Field(TSRT,AnyAcc,NoLock,Preserve) + { + DVID, 16, + Offset(0x10), + TADL, 32, + TADH, 32, + } +} + +/* Intel PSE TSN Ethernet Controller #2 0:1d.2 */ + +Device(OTN1) { + Name(_ADR, 0x001D0002) + OperationRegion(TSRT,PCI_Config,0x00,0x100) + Field(TSRT,AnyAcc,NoLock,Preserve) + { + DVID, 16, + Offset(0x10), + TADL, 32, + TADH, 32, + } +} |