diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-03-23 15:40:00 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-03-30 08:29:38 +0000 |
| commit | c0d3cf105254c0bbde5c57c8817f5263271fb0fe (patch) | |
| tree | b76d060dcb00f6696ded9e39bdc7a7808bcb1e72 /src/soc/intel/denverton_ns | |
| parent | 57351dd872746392175f5684b04ac9fb0a5d5538 (diff) | |
soc/intel: Remove blank lines before '}' and after '{'
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/bootblock/bootblock.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/gpio_dnv.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/romstage.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/smm.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/uart.c | 1 |
5 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 0846c8e474..6601714491 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -80,7 +80,6 @@ static void sanity_check_pci_mmconf(void) void bootblock_soc_early_init(void) { - #if (CONFIG(CONSOLE_SERIAL)) early_uart_init(); #endif diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 299f950968..05260bfe16 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -159,7 +159,6 @@ void gpio_configure_dnv_pads(const struct dnv_pad_config *gpio, size_t num) NumberOfGroups = V_PCH_GPIO_GROUP_MAX; for (Index = 0; Index < (uint32_t)num; Index++) { - Dw0RegMask = 0; Dw0Reg = 0; Dw1RegMask = 0; diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 8e555efff1..b55ddfb435 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -146,7 +146,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) /* if ME HECI communication is disabled, apply default one*/ if (mupd->FspmConfig.PcdMeHeciCommunication == 0) { - /* Configure FIA MUX PCD */ /* Assume the validating silicon has max lanes. */ supported_hsio_lanes = BL_ME_FIA_MUX_LANE_NUM_MAX; diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index bb399e81ca..e32ae104b8 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -32,7 +32,6 @@ void smm_southbridge_clear_state(void) static void smm_southbridge_enable(uint16_t pm1_events) { - printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events Disable PCIe wake. */ enable_pm1(pm1_events | PCIEXPWAK_DIS); diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index b8598cc4ef..ca2e67f752 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -32,7 +32,6 @@ static void dnv_ns_uart_read_resources(struct device *dev) if (res != NULL) res->flags = 0; compact_resources(dev); - } static struct device_operations uart_ops = { |