diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-16 10:37:15 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-28 22:48:00 +0000 |
| commit | 81100bf7ff62c4ee53214afb82f2fa9112d109b6 (patch) | |
| tree | 8fdb92df42e60e200095aac64eb6b9781c54594f /src/soc/intel/denverton_ns | |
| parent | 4007d7f8c73d2872c6fe74f2b58a673161d6c947 (diff) | |
soc/intel: Move fill_postcar_frame to memmap.c
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/memmap.c | 28 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/romstage.c | 26 |
2 files changed, 28 insertions, 26 deletions
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 0cca4b90d4..f7b2e07157 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -14,8 +14,10 @@ * GNU General Public License for more details. */ +#include <arch/romstage.h> #include <cbmem.h> #include <assert.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci_def.h> @@ -75,3 +77,29 @@ void smm_region(uintptr_t *start, size_t *size) *start = smm_region_start(); *size = smm_region_size(); } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, + MTRR_TYPE_WRBACK); + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index cbd451ae0d..cb6ba11386 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -151,32 +151,6 @@ void mainboard_romstage_entry(void) #endif } -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); -} - static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) { FSPM_UPD *mupd = container_of(m_cfg, FSPM_UPD, FspmConfig); |