src/soc: Fix various typos

These typos were found through manual review and grep.

Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

7 files changed, 9 insertions, 9 deletions

diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index a81b389d99..affddbaec2 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -185,7 +185,7 @@ void early_uart_init(void)
 {
 	register int i;
 
-	/* Check: do we have enought elements to init. ? */
+	/* Check: do we have enough elements to init. ? */
 	BUILD_BUG_ON(DENVERTON_UARTS_TO_INI > ELEM_OF_UART_TAB);
 
 	/* HSUART(B0:D26:0-1) GPIO init. */
diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c
index 78488835a2..7de0976854 100644
--- a/src/soc/intel/denverton_ns/csme_ie_kt.c
+++ b/src/soc/intel/denverton_ns/csme_ie_kt.c
@@ -38,7 +38,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany)
 		struct resource *resource;
 		resource = pci_get_resource(dev, index);
 		/**
-		* Workarond for Denverton-NS silicon (Rev A0/A1 for CSME/IE,
+		* Workaround for Denverton-NS silicon (Rev A0/A1 for CSME/IE,
 		*  Rev B0 for CSME only)
 		*  CSME&IEs KT IO bar must be 16-byte aligned
 		*/
@@ -59,7 +59,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany)
 static void pci_csme_ie_kt_read_resources(device_t dev)
 {
 	/**
-	* CSME/IE KT has 2 BARs to chec:
+	* CSME/IE KT has 2 BARs to check:
 	*   0x10 - KT IO BAR
 	*   0x14 - KT Memory BAR
 	* CSME/IE KT has no Expansion ROM BAR to check:
diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c
index 3030fbb98b..1921b13806 100644
--- a/src/soc/intel/denverton_ns/gpio.c
+++ b/src/soc/intel/denverton_ns/gpio.c
@@ -284,7 +284,7 @@ void gpio_configure_pads(const struct pad_config *gpio, size_t num)
 			    (GPIO_CONF_INT_ROUTE_BIT_POS + 1))
 			   << N_PCH_GPIO_RX_NMI_ROUTE);
 
-		// If CFIO is not Working as GPIO mode, Don't move TxDisabe and
+		// If CFIO is not Working as GPIO mode, Don't move TxDisable and
 		// RxDisable
 		if (GpioData->GpioConfig.PadMode == GpioPadModeGpio) {
 			//
diff --git a/src/soc/intel/denverton_ns/include/soc/bootblock.h b/src/soc/intel/denverton_ns/include/soc/bootblock.h
index 8e58529770..5136ecd494 100644
--- a/src/soc/intel/denverton_ns/include/soc/bootblock.h
+++ b/src/soc/intel/denverton_ns/include/soc/bootblock.h
@@ -16,13 +16,13 @@
 #ifndef _SOC_DENVERTON_NS_BOOTBLOCK_H_
 #define _SOC_DENVERTON_NS_BOOTBLOCK_H_
 
-/* Bootblock pre console init programing */
+/* Bootblock pre console init programming */
 //void bootblock_cpu_init(void);
 //void bootblock_pch_early_init(void);
 //void bootblock_systemagent_early_init(void);
 void early_uart_init(void);
 
-/* Bootblock post console init programing */
+/* Bootblock post console init programming */
 //void enable_smbus(void);
 //void i2c_early_init(void);
 //void pch_early_init(void);
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
index 9b63a0837c..43e0647bd0 100644
--- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
+++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
@@ -141,7 +141,7 @@
 #define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00
 #define V_PCH_GPIO_RX_PAD_STATE_INT 0x01
 
-// RX Raw Overrride to 1
+// RX Raw Override to 1
 #define B_PCH_GPIO_RX_RAW1 (1 << 28)
 #define N_PCH_GPIO_RX_RAW1 28
 #define V_PCH_GPIO_RX_RAW1_DIS 0x00
diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h
index fe6dc826d1..771c3d868a 100644
--- a/src/soc/intel/denverton_ns/include/soc/smm.h
+++ b/src/soc/intel/denverton_ns/include/soc/smm.h
@@ -47,7 +47,7 @@ enum {
 };
 
 /* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure. */
+ * 0 on success, < 0 on failure. */
 int smm_subregion(int sub, void **start, size_t *size);
 
 #if !defined(__PRE_RAM__) && !defined(__SMM___)
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index 48e81e5783..1ac0961a05 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -39,7 +39,7 @@
 #define PCH_LP_REDIR_ETR 120
 
 /**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
  *
  * @param dev PCI device with I/O APIC control registers
  */