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author | Aamir Bohra <aamir.bohra@intel.com> | 2019-12-06 19:37:37 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-11 11:38:04 +0000 |
commit | e0cdaf0b19b68644b6c398be825f94327572e056 (patch) | |
tree | f6ee82f84df13cfc0664edbbecbcdedbc61c7644 /src/soc/intel/denverton_ns | |
parent | ddb4b0d576ce8a7a8f36ce8a8ebcfb871c11b18b (diff) |
soc/intel/tigerlake: add soc implementation for ETR address API
Add soc_pmc_etr_addr function definition in tigerlake SOC code.
The function is declared in common soc intel pmc driver.
Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37555
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
0 files changed, 0 insertions, 0 deletions