diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-06-01 18:12:16 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-07-10 12:55:46 +0000 |
| commit | e7fa24470dc3b3403eabd757a87cfb993f316b1a (patch) | |
| tree | 6497bd70076905089fc81ed777cbec34486569c0 /src/soc/intel/denverton_ns | |
| parent | a9997f891facaf3c855d7f2c9c6840acbf101193 (diff) | |
cbmem_top: Change the return value to uintptr_t
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/memmap.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/systemagent.c | 4 |
3 files changed, 4 insertions, 6 deletions
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index afda045a42..207f4df31d 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -56,7 +56,7 @@ static const acpi_cstate_t cstate_map[] = { void soc_fill_gnvs(struct global_nvs *gnvs) { /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = (uintptr_t)cbmem_top(); + gnvs->tolm = cbmem_top(); /* MMIO Low/High & TSEG base and length */ gnvs->mmiob = (u32)get_top_of_low_memory(); diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index f607d0f0df..957605964e 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -41,14 +41,12 @@ void smm_region(uintptr_t *start, size_t *size) void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 6c5149bb9f..e8bcba77fb 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -240,10 +240,10 @@ static void mc_add_dram_resources(struct device *dev) reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); /* 0x100000 -> cbmem_top() */ - ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top()); + ram_from_to(dev, index++, 1 * MiB, cbmem_top()); /* cbmem_top() -> TSEG */ - mmio_from_to(dev, index++, (uintptr_t)cbmem_top(), mc_values[TSEG_REG]); + mmio_from_to(dev, index++, cbmem_top(), mc_values[TSEG_REG]); /* TSEG -> TOLUD */ reserved_ram_from_to(dev, index++, mc_values[TSEG_REG], mc_values[TOLUD_REG]); |