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authorElyes Haouas <ehaouas@noos.fr>2023-08-21 20:39:25 +0200
committerMartin L Roth <gaumless@gmail.com>2023-08-21 23:45:43 +0000
commit757509113b6b944167cf1f13f9569236cd7e5b18 (patch)
treea704133034ae50f622c9381454513145ef86d02b /src/soc/intel/denverton_ns
parenta1957314c2cb78a229ca87bd2523d24001a644a9 (diff)
soc: Remove SOC_SPECIFIC_OPTIONS
Move specific options under the boolean and remove dummy SOC_SPECIFIC_OPTIONS. Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns')
-rw-r--r--src/soc/intel/denverton_ns/Kconfig19
1 files changed, 8 insertions, 11 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index dcf9a5f0d4..55ba2cdae9 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -2,17 +2,6 @@
config SOC_INTEL_DENVERTON_NS
bool
- help
- Intel Denverton-NS SoC support
-
-if SOC_INTEL_DENVERTON_NS
-
-config CPU_INTEL_NUM_FIT_ENTRIES
- int
- default 1
-
-config CPU_SPECIFIC_OPTIONS
- def_bool y
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
@@ -50,6 +39,14 @@ config CPU_SPECIFIC_OPTIONS
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+ help
+ Intel Denverton-NS SoC support
+
+if SOC_INTEL_DENVERTON_NS
+
+config CPU_INTEL_NUM_FIT_ENTRIES
+ int
+ default 1
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000