diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-05-27 14:37:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 08:22:20 +0000 |
| commit | 6ea6775fa3eaa78b5322833940b9ba32d784556b (patch) | |
| tree | fed449179d0025ee3efcc697f1755b676fac3baa /src/soc/intel/denverton_ns | |
| parent | 089b9089c111da9175d87c4f2671ba8ebe353b4b (diff) | |
soc/{amd,intel}: Use postcar_frame_add_romcache()
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/romstage.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 7073627a79..105298e8b0 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -172,9 +172,8 @@ asmlinkage void car_stage_entry(void) MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is |