diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-07 13:40:19 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-19 09:57:47 +0000 |
| commit | 56ab8e2aae25efc839daeb56d5922e66d2680aec (patch) | |
| tree | 2790032028d9ddba711fe08a3eaab3105d571acd /src/soc/intel/denverton_ns | |
| parent | 6ac5dc2ca6a6b09d1b0156c2db6aa1385ccaf13e (diff) | |
soc/intel/common/cpu: Use SoC overrides to get CPU privilege level
This patch implements a SoC overrides to check CPU privilege level
as the MSR is not consistent across platforms.
For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR
0x151.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/cpu.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/msr.h | 2 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index fb4923f7e1..3747a48e68 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -23,6 +23,14 @@ #include <soc/soc_util.h> #include <types.h> +bool cpu_soc_is_in_untrusted_mode(void) +{ + msr_t msr; + + msr = rdmsr(MSR_POWER_MISC); + return !!(msr.lo & ENABLE_IA_UNTRUSTED); +} + static struct smm_relocation_attrs relo_attrs; static void dnv_configure_mca(void) diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 21f3e7b41f..7eb9fdce8b 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -10,6 +10,8 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) +#define MSR_POWER_MISC 0x120 +#define ENABLE_IA_UNTRUSTED (1 << 6) #define IA32_MCG_CAP 0x179 #define IA32_MCG_CAP_COUNT_MASK 0xff #define IA32_MCG_CAP_CTL_P_BIT 8 |