diff options
| author | Shelley Chen <shchen@google.com> | 2021-10-20 15:43:45 -0700 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2021-11-10 17:24:16 +0000 |
| commit | 4e9bb3308e811000eb089be6b03658e4cb9a4717 (patch) | |
| tree | dca19104e9f6144736a042203f53de9802b53a7e /src/soc/intel/denverton_ns | |
| parent | 5c163bb86926d982af1ffd93b072ca85070ca1e1 (diff) | |
Rename ECAM-specific MMCONF Kconfigs
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/acpi/northcluster.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/bootblock/bootblock.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index a84cf1eebd..0643384e91 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -44,10 +44,10 @@ config CPU_SPECIFIC_OPTIONS select FSP_T_XIP if FSP_CAR select FSP_M_XIP -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index 26a6f2ed95..e415dc4ea3 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -122,7 +122,7 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { // PCIEXBAR memory range - Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadOnly, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) // TSEG Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) }) diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 1aebab4f83..cb2503ae40 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -74,8 +74,8 @@ static void sanity_check_pci_mmconf(void) break; } - assert(base == CONFIG_MMCONF_BASE_ADDRESS); - assert(length == CONFIG_MMCONF_BUS_NUMBER); + assert(base == CONFIG_ECAM_MMCONF_BASE_ADDRESS); + assert(length == CONFIG_ECAM_MMCONF_BUS_NUMBER); } void bootblock_soc_early_init(void) |