diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-10 12:38:02 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 20:21:45 +0000 |
| commit | 34f26b298961300fe97234ac5f424f57ebd04aad (patch) | |
| tree | 9221a4e220dfacee5ecda62ee216104416933e74 /src/soc/intel/denverton_ns | |
| parent | 03c0853f4d58c73a632f81cac2eb16b759d7f338 (diff) | |
drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_" prefix.
1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.
For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.
Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.
Additionally, fixed SoC configs inclusion order alphabetically.
BUG=b:211954778
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 09c140820a..4c0c998792 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -15,17 +15,20 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DEBUG_GPIO - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_RESET - select PLATFORM_USES_FSP2_0 + select FSP_M_XIP + select FSP_T_XIP if FSP_CAR select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER - select CACHE_MRC_SETTINGS - select PCR_COMMON_IOSF_1_0 - select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE + select PCR_COMMON_IOSF_1_0 + select PLATFORM_USES_FSP2_0 + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_ACPI @@ -35,16 +38,15 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_SMBUS + select SUPPORT_CPU_UCODE_IN_CBFS select SOUTHBRIDGE_INTEL_COMMON_SMBUS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select SUPPORT_CPU_UCODE_IN_CBFS - select FSP_T_XIP if FSP_CAR - select FSP_M_XIP + select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 |