Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib"

This reverts commit ab1227226ebd78b40783cb200e60711b900352f0.

There were significant changes around soc_reset_tco_status() that this
code needs to be adapted to.

Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 13 insertions, 14 deletions

diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index e1e7bc4718..85f99d7966 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -25,7 +25,6 @@
 #include <device/pci_def.h>
 #include <elog.h>
 #include <intelblocks/fast_spi.h>
-#include <intelblocks/pmclib.h>
 #include <spi-generic.h>
 #include <soc/iomap.h>
 #include <soc/soc_util.h>
@@ -53,7 +52,7 @@ int southbridge_io_trap_handler(int smif)
 	return 0;
 }
 
-void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); }
+void southbridge_smi_set_eos(void) { enable_smi(EOS); }
 
 global_nvs_t *smm_get_gnvs(void) { return gnvs; }
 
@@ -99,7 +98,7 @@ static void southbridge_smi_sleep(void)
 	uint16_t pmbase = get_pmbase();
 
 	/* First, disable further SMIs */
-	pmc_disable_smi(SLP_SMI_EN);
+	disable_smi(SLP_SMI_EN);
 
 	/* Figure out SLP_TYP */
 	reg32 = inl((uint16_t)(pmbase + PM1_CNT));
@@ -132,7 +131,7 @@ static void southbridge_smi_sleep(void)
 		printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
 
 		/* Disable all GPE */
-		pmc_disable_all_gpe();
+		disable_all_gpe();
 
 		/* also iterates over all bridges on bus 0 */
 		busmaster_disable_on_bus(0);
@@ -146,7 +145,7 @@ static void southbridge_smi_sleep(void)
 	 * event again. We need to set BIT13 (SLP_EN) though to make the
 	 * sleep happen.
 	 */
-	pmc_enable_pm1_control(SLP_EN);
+	enable_pm1_control(SLP_EN);
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
@@ -159,7 +158,7 @@ static void southbridge_smi_sleep(void)
 	reg32 = inl((uint16_t)(pmbase + PM1_CNT));
 	if (reg32 & SCI_EN) {
 		/* The OS is not an ACPI OS, so we set the state to S0 */
-		pmc_disable_pm1_control(SLP_EN | SLP_TYP);
+		disable_pm1_control(SLP_EN | SLP_TYP);
 	}
 }
 
@@ -238,11 +237,11 @@ static void southbridge_smi_apmc(void)
 		printk(BIOS_DEBUG, "P-state control\n");
 		break;
 	case APM_CNT_ACPI_DISABLE:
-		pmc_disable_pm1_control(SCI_EN);
+		disable_pm1_control(SCI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
 	case APM_CNT_ACPI_ENABLE:
-		pmc_enable_pm1_control(SCI_EN);
+		enable_pm1_control(SCI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
 	case APM_CNT_FINALIZE:
@@ -269,23 +268,23 @@ static void southbridge_smi_apmc(void)
 
 static void southbridge_smi_pm1(void)
 {
-	uint16_t pm1_sts = pmc_clear_pm1_status();
+	uint16_t pm1_sts = clear_pm1_status();
 
 	/* While OSPM is not active, poweroff immediately
 	 * on a power button event.
 	 */
 	if (pm1_sts & PWRBTN_STS) {
 		// power button pressed
-		pmc_disable_pm1_control(-1UL);
-		pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+		disable_pm1_control(-1UL);
+		enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
 	}
 }
 
-static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); }
+static void southbridge_smi_gpe0(void) { clear_gpe_status(); }
 
 static void southbridge_smi_tco(void)
 {
-	uint32_t tco_sts = pmc_clear_tco_status();
+	uint32_t tco_sts = clear_tco_status();
 
 	/* Any TCO event? */
 	if (!tco_sts)
@@ -355,7 +354,7 @@ void southbridge_smi_handler(void)
 	/* We need to clear the SMI status registers, or we won't see what's
 	 * happening in the following calls.
 	 */
-	smi_sts = pmc_clear_smi_status();
+	smi_sts = clear_smi_status();
 
 	/* Call SMI sub handler for each of the status bits */
 	for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {