diff options
| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2017-11-06 13:19:58 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-11-07 12:32:53 +0000 |
| commit | f528195bdf141e84d3121411d2cbe32f5938dd72 (patch) | |
| tree | cdf9d04eaa51ebae051ca825b8cfdd61ea62c4d9 /src/soc/intel/denverton_ns/romstage.c | |
| parent | 6a8118405821815017d780d953260bc48eb90e6d (diff) | |
soc/intel/denverton_ns: re-factor HSIO configuration
The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.
Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns/romstage.c')
| -rw-r--r-- | src/soc/intel/denverton_ns/romstage.c | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 512d8ccb3c..e0286f3f01 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 - 2017 Intel Corp. + * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,8 +17,6 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <harcuvar_boardid.h> -#include <hsio.h> #include <reset.h> #include <soc/fiamux.h> #include <soc/iomap.h> @@ -237,7 +236,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) FSPM_UPD *mupd = container_of(m_cfg, FSPM_UPD, FspmConfig); size_t num; uint16_t supported_hsio_lanes; - uint8_t boardid = board_id(); BL_HSIO_INFORMATION *hsio_config; /* Set the parameters for MemoryInit */ @@ -250,17 +248,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) /* Assume the validating silicon has max lanes. */ supported_hsio_lanes = BL_ME_FIA_MUX_LANE_NUM_MAX; - switch (boardid) { - case BoardIdHarcuvar: - num = ARRAY_SIZE(harcuvar_hsio_config); - hsio_config = - (BL_HSIO_INFORMATION *)harcuvar_hsio_config; - break; - default: - num = 0; - hsio_config = NULL; - break; - } + num = mainboard_get_hsio_config(&hsio_config); if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config)) |