diff options
| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-29 11:36:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-14 21:03:17 +0000 |
| commit | 3ac3a68eef7ebd14cee7e09e22f02a8f6ce54f24 (patch) | |
| tree | 97de336fd9e5a83956802cfdec0afae336382c34 /src/soc/intel/denverton_ns/include | |
| parent | 7ebb6b0f00ed6b8f92749cc4b035f02c001197e7 (diff) | |
soc/intel/denverton_ns: port gpio to intelblock
The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.
Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns/include')
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/gpio.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h new file mode 100644 index 0000000000..082de218fd --- /dev/null +++ b/src/soc/intel/denverton_ns/include/soc/gpio.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Online SAS + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _SOC_DENVERTON_NS_GPIO_H_ +#define _SOC_DENVERTON_NS_GPIO_H_ + +#include <soc/gpio_defs.h> + +#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */ + +#define GPIO_MAX_NUM_PER_GROUP 32 + + +#define NUM_NC_GPI_REGS \ + (ALIGN_UP(V_PCH_GPIO_NC_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ + / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_SC_DFX_GPI_REGS \ + (ALIGN_UP(V_PCH_GPIO_SC_DFX_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ + / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_SC0_GPI_REGS \ + (ALIGN_UP(V_PCH_GPIO_SC0_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ + / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_SC1_GPI_REGS \ + (ALIGN_UP(V_PCH_GPIO_SC1_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ + / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPI_STATUS_REGS (NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS +\ + NUM_SC0_GPI_REGS + NUM_SC1_GPI_REGS) + + +#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ + +#include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in + lines above and soc/gpio_defs.h */ + +#endif /* _SOC_DENVERTON_NS_GPIO_H_ */ |