diff options
| author | Mariusz Szafranski <mariuszx.szafranski@intel.com> | 2017-08-02 17:28:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-09-05 13:39:54 +0000 |
| commit | a404133547c98094a326f60b83e1576ba94b8c06 (patch) | |
| tree | 59847d084c0462833878627491cfbf3e67fca4af /src/soc/intel/denverton_ns/chip.h | |
| parent | 84c4987eae9f8686e6d92e38ee18744d69576f2d (diff) | |
soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC
This change adds support for Intel Atom C3000 SoC
("Denverton" and "Denverton-NS").
Code is partially based on Apollo Lake/Skylake code.
Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/chip.h')
| -rw-r--r-- | src/soc/intel/denverton_ns/chip.h | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h new file mode 100644 index 0000000000..bfa6a0132f --- /dev/null +++ b/src/soc/intel/denverton_ns/chip.h @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 - 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef SOC_INTEL_DENVERTON_NS_CHIP_H +#define SOC_INTEL_DENVERTON_NS_CHIP_H + +struct soc_intel_denverton_ns_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + /** + * Device Interrupt Routing configuration + * Interrupt Pin x Route. + * 0h = PIRQA# + * 1h = PIRQB# + * 2h = PIRQC# + * 3h = PIRQD# + * 4h = PIRQE# + * 5h = PIRQF# + * 6h = PIRQG# + * 7h = PIRQH# + */ + uint16_t ir00_routing; + uint16_t ir01_routing; + uint16_t ir02_routing; + uint16_t ir03_routing; + uint16_t ir04_routing; + uint16_t ir05_routing; + uint16_t ir06_routing; + uint16_t ir07_routing; + uint16_t ir08_routing; + uint16_t ir09_routing; + uint16_t ir10_routing; + uint16_t ir11_routing; + uint16_t ir12_routing; + + /** + * Device Interrupt Polarity Control + * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + */ + uint32_t ipc0; + uint32_t ipc1; + uint32_t ipc2; + uint32_t ipc3; +}; + +extern struct chip_operations soc_intel_denverton_ns_ops; + +typedef struct soc_intel_denverton_ns_config config_t; + +#endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */ |