diff options
| author | Uwe Poeche <uwe.poeche@siemens.com> | 2022-05-23 12:06:28 +0200 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-06-03 15:22:17 +0000 |
| commit | d2d90215435f05329bfc03d9351ee6f8f5351014 (patch) | |
| tree | 7522c210c6219c6aa81ca3a941be05443d3c0c59 /src/soc/intel/common | |
| parent | 8da4bfe5b573f395057fbfb5a9d99b376e25c2a4 (diff) | |
intel/common/block: move RAPL disabling to common code
This patch brings the feature of disabling RAPL to common code. It
replaces the current solution for APL and EHL.
For special case if RAPL disabling is only working via changes in MCHBAR
a new config switch was introduced.
Test: Boot mc_apl4/5 with this patch and ensure that the
relevant bits in MSR 0x610 are the same as before the
patch.
Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/power_limit/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/common/block/power_limit/power_limit.c | 17 |
2 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/power_limit/Kconfig b/src/soc/intel/common/block/power_limit/Kconfig index 5b2b34885f..b6782bc6df 100644 --- a/src/soc/intel/common/block/power_limit/Kconfig +++ b/src/soc/intel/common/block/power_limit/Kconfig @@ -3,3 +3,9 @@ config SOC_INTEL_COMMON_BLOCK_POWER_LIMIT default n help This option allows to configure processor power limit values. + +config SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR + bool + default n + help + Select if disabling Running Average Power Limit (RAPL) has to be done via MCHBAR. diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index 417dd04672..dce174b38a 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -77,6 +77,23 @@ void set_power_limits(u8 power_limit_1_time, unsigned int power_unit; unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; + uint32_t value; + + if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) { + printk(BIOS_INFO, "Disabling RAPL\n"); + if (CONFIG(SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR)) { + value = MCHBAR32(MCH_PKG_POWER_LIMIT_LO); + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = value & ~(PKG_POWER_LIMIT_EN); + value = MCHBAR32(MCH_PKG_POWER_LIMIT_HI); + MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = value & ~(PKG_POWER_LIMIT_EN); + } else { + msr = rdmsr(MSR_PKG_POWER_LIMIT); + msr.lo &= ~PKG_POWER_LIMIT_EN; + msr.hi &= ~PKG_POWER_LIMIT_EN; + wrmsr(MSR_PKG_POWER_LIMIT, msr); + } + return; + } if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = |