diff options
| author | John Su <john_su@compal.corp-partner.google.com> | 2018-11-06 10:51:43 +0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-11-07 15:58:11 +0000 |
| commit | 85376bfd9b018820e84fec92471d13717ad14083 (patch) | |
| tree | 8614cbc1dc39098c3ccb205b81468157cda29f8f /src/soc/intel/common | |
| parent | 63952e10601307d1f2034e9db7cc50f90cb24ed5 (diff) | |
soc/intel/apollolake: Provide interface to update TCC offset
This change provides an interface for apollolake to set TCC before
BIOS reset complete happens in romstage.
With this change, we can add code to update Tcc in devicetree.
BUG=b:117789732
TEST=Match the result from TAT UI
Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 09f0fce1a8..622eb071fb 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -20,26 +20,26 @@ #define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ -#define PKG_C_STATE_LIMIT_C2_MASK 0x2 +#define PKG_C_STATE_LIMIT_C2_MASK 0x2 /* Set MSR_PKG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ -#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 /* Set MSR_PKG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ -#define IO_MWAIT_REDIRECT_MASK 0x400 +#define IO_MWAIT_REDIRECT_MASK 0x400 /* Set MSR_PKG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ -#define CST_CFG_LOCK_MASK 0x8000 +#define CST_CFG_LOCK_MASK 0x8000 #define MSR_BIOS_UPGD_TRIG 0x7a #define SGX_ACTIVATE_BIT (1) #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_POWER_MISC 0x120 -#define ENABLE_IA_UNTRUSTED (1 << 6) -#define FLUSH_DL1_L2 (1 << 8) +#define ENABLE_IA_UNTRUSTED (1 << 6) +#define FLUSH_DL1_L2 (1 << 8) #define MSR_EMULATE_PM_TMR 0x121 -#define EMULATE_DELAY_OFFSET_VALUE 20 -#define EMULATE_PM_TMR_EN (1 << 16) -#define EMULATE_DELAY_VALUE 0x13 +#define EMULATE_DELAY_OFFSET_VALUE 20 +#define EMULATE_PM_TMR_EN (1 << 16) +#define EMULATE_DELAY_VALUE 0x13 #define MSR_FEATURE_CONFIG 0x13c -#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL -#define FEATURE_CONFIG_LOCK (1 << 0) +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) @@ -49,9 +49,11 @@ /* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) #define MSR_TEMPERATURE_TARGET 0x1a2 +#define TEMPERATURE_TCC_MASK 0xf +#define TEMPERATURE_TCC_SHIFT 24 #define MSR_PREFETCH_CTL 0x1a4 -#define PREFETCH_L1_DISABLE (1 << 0) -#define PREFETCH_L2_DISABLE (1 << 2) +#define PREFETCH_L1_DISABLE (1 << 0) +#define PREFETCH_L2_DISABLE (1 << 2) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MISC_PWR_MGMT_ISST_EN (1 << 6) @@ -80,7 +82,7 @@ * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. */ -#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e +#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e #define MSR_PKG_POWER_SKU 0x614 #define MSR_DDR_RAPL_LIMIT 0x618 #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 |