diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-09-18 17:08:48 +0200 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-21 14:47:42 +0000 |
| commit | 841416f6f8318f65982c29d376fce2e810045b8d (patch) | |
| tree | b4adec1b0370ec4acdb9771984b30fd9c9dac0e8 /src/soc/intel/common | |
| parent | 09703f64940a66345f27d28c0e339c7ac1864b54 (diff) | |
soc/intel/apollolake: Make SCI configurable
The System Control Interrupt is routed per default to IRQ 9. Some
mainboards use IRQ 9 for different purpose. Therefore it is necessary to
make the SCI configurable on Apollo Lake.
Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/acpi.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 010773b52a..85e6ca3c6e 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Intel Corp. + * Copyright 2017 Siemens AG. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,9 @@ struct global_nvs_t; /* Read the scis from soc specific register. Returns int scis value */ uint32_t soc_read_sci_irq_select(void); +/* Write the scis from soc specific register. */ +void soc_write_sci_irq_select(uint32_t scis); + /* * Calls acpi_write_hpet which creates and fills HPET table and * adds it to the RSDT (and XSDT) structure. |