diff options
author | Aaron Durbin <adurbin@chromium.org> | 2015-09-09 17:05:06 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-10 17:52:28 +0000 |
commit | 789f2b6c435c7f31591e2c5e969ba96df21a191d (patch) | |
tree | 065bb61fb3c35d9e6ee97ff676ce1b9bdfa6ea0d /src/soc/intel/common | |
parent | 95ba4c87f5f4802e2afaeae38003db5e7235864a (diff) |
fsp1_1: provide binding to UEFI version
FSP has some unique attributes which makes integration
cumbersome:
1. FSP header files do not include the types they need. Like
EDKII development it's expected types are provided by the
build system. Therefore, one needs to include the proper
files to avoid compilation issues.
2. An implementation of FSP for a chipset may use different
versions of the UEFI PI spec implementation. EDKII is a
proxy for all of UEFI specifications. In order to provide
flexibility one needs to binding a set of types and
structures from an UEFI PI implementation.
3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
file which defines it's own types. Commonality between
FSP chipset implementations are only named typedef
structs. The fields within are not consistent. And
because of FSP's insistence on typedefs it makes it
near impossible to forward declare structs.
The above 3 means one needs to include the correct UEFI
type bindings when working with FSP. The current
implementation had the SoC picking include paths in the
edk2 directory and using a bare <uefi_types.h> include.
Also, with the prior fsp_util.h implementation the SoC's
FSP FspUpdVpd.h header file was required since for providing
all the types at once (Generic FSP 1.1 and SoC types).
The binding has been changed in the following manner:
1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
selects. No other bindings are currently available,
but this provides the policy.
2. Based on CONFIG_UEFI_2_4_BINDING the proper include
paths are added to the CPPFLAGS_common.
3. SoC Makefile.inc does not bind UEFI types nor does
it adjust CPPFLAGS_common in any way.
4. Provide a include/fsp directory under fsp1_1 and
expose src/drivers/intel/fsp1_1/include in the
include path. This split can allow a version 2,
for example, FSP to provide its own include files.
Yes, that means there needs to be consistency in
APIs, however that's not this patch.
5. Provide a way for code to differentiate the FSP spec
types (fsp/api.h) from the chipset FSP types
(fsp/soc_binding.h). This allows for code re-use that
doesn't need the chipset types to be defined such as
the FSP relocation code.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted on glados.
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Change-Id: I894165942cfe36936e186af5221efa810be8bb29
Reviewed-on: http://review.coreboot.org/11606
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r-- | src/soc/intel/common/fsp_ramstage.c | 2 | ||||
-rw-r--r-- | src/soc/intel/common/raminit.c | 2 | ||||
-rw-r--r-- | src/soc/intel/common/ramstage.h | 2 | ||||
-rw-r--r-- | src/soc/intel/common/romstage.h | 2 | ||||
-rw-r--r-- | src/soc/intel/common/vbt.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c index 41c0b1c312..d1f2e49aff 100644 --- a/src/soc/intel/common/fsp_ramstage.c +++ b/src/soc/intel/common/fsp_ramstage.c @@ -22,7 +22,7 @@ #include <cbmem.h> #include <cbfs.h> #include <console/console.h> -#include <fsp_util.h> +#include <fsp/util.h> #include <lib.h> #include <soc/intel/common/memmap.h> #include <soc/intel/common/ramstage.h> diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c index ddf567591d..bdb23e2b64 100644 --- a/src/soc/intel/common/raminit.c +++ b/src/soc/intel/common/raminit.c @@ -19,7 +19,7 @@ #include <cbmem.h> #include <console/console.h> -#include <fsp_util.h> +#include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> #include <soc/intel/common/memmap.h> diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h index 414142a8ae..d6cb895174 100644 --- a/src/soc/intel/common/ramstage.h +++ b/src/soc/intel/common/ramstage.h @@ -21,7 +21,7 @@ #ifndef _INTEL_COMMON_RAMSTAGE_H_ #define _INTEL_COMMON_RAMSTAGE_H_ -#include <fsp_util.h> +#include <fsp/util.h> #include <soc/intel/common/util.h> #include <stdint.h> diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h index 440cad75f5..b35ff6652a 100644 --- a/src/soc/intel/common/romstage.h +++ b/src/soc/intel/common/romstage.h @@ -24,7 +24,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <memory_info.h> -#include <fsp_util.h> +#include <fsp/util.h> #include <soc/intel/common/util.h> #include <soc/pei_data.h> #include <soc/pm.h> /* chip_power_state */ diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 0e46b70977..b12ec04712 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -20,7 +20,7 @@ #include <cbfs.h> #include <console/console.h> -#include <fsp_util.h> +#include <fsp/util.h> #include <lib.h> #include <soc/intel/common/ramstage.h> #include <string.h> |