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authorSubrata Banik <subrata.banik@intel.com>2021-03-25 11:05:14 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-03-27 04:22:11 +0000
commit5558f7ba0f35b79772beeb3649a33012b7d13a3f (patch)
tree852359c00997cca0ae1dfc5d9fee8dddb299c17d /src/soc/intel/common
parent6efc764c045d28d433b39e44c850605b7ed1f4a8 (diff)
soc/intel/alderlake: Correct GPE DWx assignment as per EDS
List of changes: 1. Update GPIO Group to GPE DWx assignment encoding as per MISCCFG register per GPIO Community. 2. PMC_GPP_* macros are also updated as per GPIO_CFG register in PMC space. BUG=b:183464235 TEST=Able to fix the TPM IRQ issue on SM. Change-Id: Id9f57b0b5726315f5ebba013f11d52ed3ee34484 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51789 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
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