diff options
| author | Gang Chen <gang.c.chen@intel.com> | 2024-06-18 06:39:12 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-11-14 14:29:23 +0000 |
| commit | 3d32f915a9c4d60046574690db966d1f14eebe65 (patch) | |
| tree | 79cb2533cca5fb7fa593bc77ac23b5873268eba2 /src/soc/intel/common | |
| parent | 97412d1929e88a929f73a229e40ca85a38168d7e (diff) | |
soc/intel/xeon_sp: Reserve PRMRR
PRMRR (Protected Region Memory Range Region) are not accessible as
normal DRAM regions and needs to be explicitly reserved in memory
map.
Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index a03032899d..4bdd90c536 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -55,6 +55,7 @@ #define PWR_PERF_PLATFORM_OVR (1 << 18) #define VR_THERM_ALERT_DISABLE_LOCK (1 << 23) #define MSR_PRMRR_BASE_0 0x2a0 +#define MSR_PRMRR_BASE(reg) (MSR_PRMRR_BASE_0 + (reg)) #define MSR_EVICT_CTL 0x2e0 #define MSR_LT_CONTROL 0x2e7 #define LT_CONTROL_LOCK (1 << 0) |