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authorMichael Niewöhner <foss@mniewoehner.de>2019-09-22 13:27:20 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-04-21 09:18:30 +0000
commit3c20cba28930ff86eb65074fc8cb577873901592 (patch)
tree67bde77adf0d3de6ea19edc3e5adbf7fed53ef7c /src/soc/intel/common
parentb48e6357e823dd6b01c9a0c9122079489ce8f190 (diff)
soc/intel/common/smbus: lock TCO base address on PCH finalize
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/smbus/tco.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
index 8cde3bf7f2..518541b1ab 100644
--- a/src/soc/intel/common/block/smbus/tco.c
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -24,6 +24,7 @@
#define TCOBASE 0x50
#define TCOCTL 0x54
#define TCO_BASE_EN (1 << 8)
+#define TCO_BASE_LOCK (1 << 0)
/* Get base address of TCO I/O registers. */
static uint16_t tco_get_bar(void)
@@ -52,6 +53,10 @@ void tco_write_reg(uint16_t tco_reg, uint16_t value)
void tco_lockdown(void)
{
uint16_t tcocnt;
+ const pci_devfn_t dev = PCH_DEV_SMBUS;
+
+ /* TCO base address lockdown */
+ pci_or_config32(dev, TCOCTL, TCO_BASE_LOCK);
/* TCO Lock down */
tcocnt = tco_read_reg(TCO1_CNT);