diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-04-01 16:27:55 +0530 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-04-06 19:32:28 +0000 |
| commit | 39b7665abe1c5356e0248eddccbd7711ad377ad7 (patch) | |
| tree | c1ede15552d50f825642193c561264e745d3ec4d /src/soc/intel/common | |
| parent | f5ae1dd1be35daf3012e5773e7ce05f95ffa4da6 (diff) | |
soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
In Intel designs, internal processor errors, such as a processor
instruction retirement watchdog timeout (also known as a 3-strike
timeout) will cause a CATERR assertion and can only be recovered from by
a system reset.
This patch prevents the Three Strike Counter from incrementing (as per
Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cpulib.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 1 |
3 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index bfa4818450..3f0ee674f4 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -569,3 +569,12 @@ unsigned int smbios_cpu_get_max_speed_mhz(void) { return cpu_get_max_turbo_ratio() * CONFIG_CPU_BCLK_MHZ; } + +void disable_three_strike_error(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PREFETCH_CTL); + msr.lo = msr.lo | DISABLE_CPU_ERROR; + wrmsr(MSR_PREFETCH_CTL, msr); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index c72e1eaed9..38c43d8c8f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -222,4 +222,11 @@ bool is_sgx_supported(void); * Returns true if Key Locker feature is supported otherwise false. */ bool is_keylocker_supported(void); + +/* + * This function prevents the Three Strike Counter from incrementing. + * It helps to collect more useful CPU traces for debugging. + */ +void disable_three_strike_error(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index d4d8732418..9f95e9f7e6 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -35,6 +35,7 @@ #define MSR_PREFETCH_CTL 0x1a4 #define PREFETCH_L1_DISABLE (1 << 0) #define PREFETCH_L2_DISABLE (1 << 2) +#define DISABLE_CPU_ERROR (1 << 11) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MISC_PWR_MGMT_ISST_EN (1 << 6) |